Wiring structure and formation method thereof for semiconductor

Details Wiring structure and formation method thereof for semiconductor Wiring structure and formation method thereof for semiconductor

1998-05-15

2000-05-16

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257774, 257758, H01L 2348

Patent

active

060641193

ABSTRACT:
A wiring structure of a semiconductor device includes a substrate; a first conductive layer formed in the substrate; an insulation film formed on the substrate including the first conductive layer and having a contact hole therein through which the upper surface of the first conductive layer is exposed, wherein the contact hole includes an upper contact hole and a lower contact hole having a shape undercut into the insulation film and thus being wider than the upper contact hole; and a second conductive layer formed on the insulation film so as to thoroughly fill the contact hole and electrically connected to the first conductive layer.

REFERENCES:
patent: 4541169 (1985-09-01), Bartush
patent: 4556897 (1985-12-01), Yorikane et al.
patent: 5130764 (1992-07-01), Cetronio et al.
patent: 5219792 (1993-06-01), Kim et al.
patent: 5266525 (1993-11-01), Morozumi
R. Cullet, Process for Interconnecting Different Levels of Metal in an Integrated Circuit. IBM Technical Disclosure Bulletin, vol. 21 No. 7, pp. 2850-2851, Dec. 1978.
Anonymous, Reducing stresses in asymmetrical studs on silicon chips using sacrificial studs, Research Disclosure, No. 340, England, Aug. 1992.

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