Wiring pattern of semiconductor integrated circuit device

Details Wiring pattern of semiconductor integrated circuit device Wiring pattern of semiconductor integrated circuit device

1998-06-04

2001-02-20

Fears, Terrell W. (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C361S052000

Reissue Patent

active

RE037059

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to wiring pattern of a semiconductor integrated circuit device, and more particularly to the technique of matching the allowance between a connection hole, such as a contact hole or through hole, and a wiring.
2. Description of the Related Art
conventionally, the matching allowance between a connecting hole (e.g., a contact hole or a through hole) and a wiring is set equally around the connecting holes, in order to compensate for the deviation which occurs in the step of lithography, randomly in every direction. When the deviation is zero, the width of the wiring around the connection hole, the around width H, at the periphery of the connecting hole is formed as shown in
FIGS. 1A and 1B
.
FIGS. 1A and 1B
illustrate a connecting hole
11
, wiring layer
12
, and an inter-layer insulation layer
13
.
As is shown in
FIG. 1B
, a notch S is formed in the wiring layer in the connection hole
11
. When electric current flows through the connection hole
11
, resistance against the current increases at the section where the notch S is located. The wiring resistance around connection hole
11
(to be called “connection hole resistance” hereinafter) can be substituted with an equivalent circuit shown in
FIG. 2
, which is designed so that when a deviation between the connection hole
11
and the pattern of the wiring
12
is zero, current paths I
2
and I
2
′ on the wiring extension side become wide.
In reality, however, due to a matching error &agr; in the step of pattern matching, a variety of deviations may occur between the connection hole
11
and the wiring layer
12
.
FIGS. 3A
to
3
C illustrate several examples of matching deviation between the connection hole
11
and the wiring layer
12
.
FIG. 3A
shows a case where the connection hole
11
deviates in the direction opposite to the wiring extension side. In this case, as the around width B
1
narrows, resistances R
3
and R
3
′ inevitably increase. However, electrical current i
3
, which is affected by the resistances, comprise a very small portion of the total current. Further, as the around width B
2
widens, resistances R
2
and R
2
′ decrease. Therefore there is little change in connection hole resistance as a whole.
FIG. 3B
shows a case where the connection hole
11
deviates in the vertical direction toward the wiring extension side. In this case, around width C
1
narrows and around width C
2
widens. Therefore resistances (R
2
+R
3
) and (R
2
′+R
3
′) respectively increase and decrease, thereby canceling each other, so that the connection hole resistance is only slightly affected, as a whole.
FIG. 3C
shows a case where the connection hole
11
deviates towards the wiring extension side. In this case, around width B
2
narrows, and the effective current paths I
2
and I
2
′ narrow, whereby the connection hole resistance inevitably increases. More specifically, current flows through all of resistances r
1
, R
2
and R
3
. As around width B
2
narrows, currents I
2
and I
2
′ flowing through resistances R
2
and R
2
′ decrease, and current i
1
flowing through resistance r
1
, which becomes high due to device structure, increases. Therefore, the matching deviation directly affects the connection hole resistance, and disconnection of the wiring due to heat-emission or electromigration may occur at the notch S.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a wiring pattern of a semiconductor integrated circuit device in which the connection hole resistance does not increase even if matching deviation between a connection hole such, as a contact hole or through hole, and a wiring layer occurs.
To achieve the above-mentioned object, the wiring pattern of the semiconductor integrated circuit device according to the present invention comprises a wiring portion extending from the connection hole and a connection portion located above the connection hole and connected to the wiring portion so that it makes an obtuse angle, in which a matching allowance for the connection hole on the wiring portion side is formed wider than the regular matching allowance by a predetermined width with which a required yield of successful matching can be assured.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4196443 (1980-04-01), Dingwell
patent: 4381215 (1983-04-01), Reynolds et al.
patent: 4482914 (1984-11-01), Mano et al.
patent: 4812419 (1989-03-01), Lee et al.
patent: 5072411 (1991-12-01), Yamaki
patent: 5126819 (1992-06-01), Abe et al.
patent: 5138700 (1992-08-01), Kinoshita
patent: 5140693 (1992-08-01), Nimomiya
patent: 5411916 (1995-05-01), Abe et al.
patent: 0166344 (1986-01-01), None
patent: 0289274 (1988-04-01), None
patent: 0414412 A2 (1990-08-01), None
patent: 2029097 (1980-03-01), None
patent: 57-201171 (1982-12-01), None
patent: 59014649 (1984-01-01), None
patent: 59169150 (1984-09-01), None
patent: 59-188149 (1984-10-01), None
patent: 60-208845 (1985-10-01), None
patent: 60242643 (1985-12-01), None
patent: 61131469 (1986-06-01), None
patent: 61-194848 (1986-08-01), None
patent: 63-78554 (1988-04-01), None
patent: 63-292672 (1988-11-01), None
patent: 1-305531 (1989-12-01), None
R.E. Oakley et al. “Pillars—The Way to Two Micron Pitch Multilevel Metallization” IEEE VLSI Multilevel Interconnection Conference Proceedings Jun. 21-24, 1984 pp. 23-29.
R.R. Joseph et al., “Reduced Electromigration Damage at AL Contacts to Si Integrated Circuits,” IBM Technical Disclosure Bulletin, vol. 15, No. 2 Aug., 1972 pp. 725-726.
S.M. Sze, Semiconductor Devices, Physics and Technology, 486-488, (1985).

Affiliated with

Also associated with

Rating

Wiring pattern of semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wiring pattern of semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wiring pattern of semiconductor integrated circuit device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2570983