Wiring pattern of semiconductor integrated circuit device

Details Wiring pattern of semiconductor integrated circuit device Wiring pattern of semiconductor integrated circuit device

1990-11-06

1992-06-30

James, Andrew J.

357 65, H01L 2188, H01L 2190

Patent

active

051268191

ABSTRACT:
As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

REFERENCES:
patent: 4381215 (1983-04-01), Reynolds et al.
patent: 4482914 (1984-11-01), Mano et al.
R. R. Joseph et al., "Reduced Electromigration Damage at AL Contacts to SI Integrated Circuits", IBM TDB, vol. 15, No. 2, Aug. 1972, pp. 725-726.
R. E. Oakley, et al., "Pillars-The Way to Two Micron Pitch Multilevel Metallisation," IEEE VLSI Multilevel Interconnection Conference Proceedings, Jun. 21-22, 1984, pp. 23-29.

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