Wiring pattern of semiconductor integrated circuit device

Details Wiring pattern of semiconductor integrated circuit device Wiring pattern of semiconductor integrated circuit device

1995-01-20

1996-06-04

Nguyen, Viet Q.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257773, 257775, 257734, 257735, 257784, H01L 2188

Patent

active

055236278

ABSTRACT:
As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

REFERENCES:
patent: 4196443 (1980-04-01), Dingwall
patent: 4381215 (1983-04-01), Reynolds et al.
patent: 4482914 (1984-11-01), Mano et al.
patent: 4812419 (1989-03-01), Lee et al.
patent: 5072411 (1991-12-01), Yamaki
patent: 5126819 (1992-06-01), Abe et al.
patent: 5138700 (1992-08-01), Kinoshita
patent: 5140693 (1992-08-01), Ninomiya
patent: 5411916 (1995-05-01), Abe et al.
R. E. Oakley et al., "Pillars--The Way to Two Micron Pitch Multilevel Metallisation" IEEE VLSI Multilevel Interconnection Conference Proceedings Jun. 21-22, 1984, pp. 23-29.
R. R. Joseph et al., "Reduced Electromigration Damage at AL Contacts to Si Integrated Circuits", IBM Technical Disclosure Bulletin, vo. 15, No. 2 Aug., 1972. pp. 725-726.

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