Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2002-09-27
2004-03-30
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S666000, C257S698000, C257S737000, C257S784000, C257S773000, C257S786000, C438S106000, C438S108000
Reexamination Certificate
active
06713869
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to a wiring pattern of semiconductor device, precisely an arrangement of wiring pad on the printed board coupled to a semiconductor chip via bonding wire.
2. Description of the Related Art
Recently There is a demand for making a semiconductor device smaller and thinner. To ask this kind of demand, a chip-scale package is developed that a semiconductor chip which has the same size of a printed board is arranged on the board. Moreover, in a semiconductor device which is going to realize high-integrated, high-performance, high-capacity, it is used a small Ball-Grid-Array type semiconductor package. In this kind of package, a semiconductor chip is coupled to the board by wire bonding or beam-lead bonding.
FIG. 1
shows an schematic view of conventional semiconductor package. As shown in
FIG. 1
, semiconductor chip
1
has plurality of electrode pad
2
. This semiconductor chip
1
is arranged on a sheet-shaped board
4
including opening
3
, its surface semiconductor device is formed is faced to the board
4
. At this point, the semiconductor chip
1
is arranged so as the electrode pad
2
to exposed from the opening
3
. The semiconductor chip is bonded to the board
4
by adhesives
5
, elastomer for instance.
FIG. 2
is a plan view of a bottom side of the semiconductor device shown in FIG.
1
and the electrode pad
2
and the wiring pattern
7
is magnified. As shown in
FIG. 2
the wiring pattern
7
coupled to the external coupling terminal
8
includes a wiring line
7
a
and connection pad
7
b
nearby the opening
3
. A pitch of the connection pad
7
b
is as same as that of the electrode pad
2
. Consequently, this connection pad
7
b
is almost perpendicular to a direction of arrangement of the electrode pad
2
. The connection pad
7
b
is coupled to the electrode pad
2
exposed from the opening
3
by bonding wire
6
. This bonding wire
6
is also perpendicular to a direction of arrangement of the electrode pad
2
.
BRIEF SUMMARY OF THE INVENTION
A semiconductor of this invention includes a electrode pad arranged on a semiconductor chip, a bonding wire, one end of which is coupled to said electrode pad, a connection pad, which another end of said bonding wire is coupled to, a pitch of which is larger than that of said electrode pad, and aligning parallel to a aligning direction of bonding wire.
REFERENCES:
patent: 5998236 (1999-12-01), Roeder et al.
patent: 6160313 (2000-12-01), Takashima et al.
patent: 6190943 (2001-02-01), Lee et al.
patent: 6214641 (2001-04-01), Akram
patent: 6218202 (2001-04-01), Yew et al.
patent: 6271056 (2001-08-01), Farnworth et al.
patent: 6300163 (2001-10-01), Akram
patent: 6300165 (2001-10-01), Castro
patent: 6326700 (2001-12-01), Bai et al.
patent: 6429528 (2002-08-01), King et al.
patent: 6531335 (2003-03-01), Grigg
patent: 6537850 (2003-03-01), Corisis
patent: 6602803 (2003-08-01), Yew et al.
patent: 6630730 (2003-10-01), Grigg
patent: 05-211191 (1993-08-01), None
Iijima Toshitsune
Kusakabe Takeshi
Hogan & Hartson LLP
Luu Chuong A
Smith Matthew
LandOfFree
Wiring pattern of semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wiring pattern of semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wiring pattern of semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3268945