Wiring pattern for a semiconductor integrated circuit device

Details Wiring pattern for a semiconductor integrated circuit device Wiring pattern for a semiconductor integrated circuit device

1998-07-09

1999-11-02

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257207, 257208, 257211, H01L 2710

Patent

active

059775734

ABSTRACT:
In a C-MOS type output circuit, desired connections between a P-MOS transistor and an N-MOS transistor are achieved without forming a third wiring layer. In a semiconductor integrated circuit device in which a group of P-MOS transistors and a group of N-MOS transistors are formed on a semiconductor substrate, in which the transistors are arranged with their channel length aligned with the direction in which free space is available within the semiconductor chip, and in which the transistors are connected in a predetermined manner with wiring patterns laid on the semiconductor substrate, a power source line and a ground line, each formed as a wiring pattern in a second wiring layer, each have a portion thereof separated from a remaining portion thereof by a circular groove so that an isolated wiring region is formed within each of the power source line and the ground line so as to be connected, by way of a via hole, to wiring patterns that are formed linearly and parallel to one another in a first wiring layer to connect between the group of P-MOS transistors and the group of N-MOS transistors.

REFERENCES:
patent: 5619048 (1997-04-01), Yokota et al.
patent: 5764533 (1998-06-01), deDood

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