Wiring or conductor interconnect for a semiconductor device or t

Details Wiring or conductor interconnect for a semiconductor device or t Wiring or conductor interconnect for a semiconductor device or t

1989-09-22

1992-04-21

James, Andrew J.

Static information storage and retrieval

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357 59, 357 231, 365154, H01L 2702

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active

051073226

ABSTRACT:
A wiring or conductor structure for an integrated circuit structure of a semiconductor device is designed to provide for extended values in integrated passive components, for example, resistance values in a memory cell of a high resistance load type static RAM. Extended values of high resistance polycrystalline silicon resistances formed in conductor films are achieved by effectively increasing the length of the films and, therefore, the regions of resistance without changing or increasing the size or scale of the semiconductor device. This is accomplished by employing double wiring or conductor layers which are electrically connected permitting a lateral extension of the integrated and patterned resistance region in at least one of the wiring layers while retaining or further reducing the integration scale of the active and passive components comprising the integrated circuit structure.

REFERENCES:
patent: 4805147 (1989-02-01), Yamanaka et al.
patent: 4853894 (1989-08-01), Yamanaka et al.
Y. Sakai, "CMOS-SRAM Process Device Technology", 28th Semiconductor Training Course, Institute of Electronics, Information & Communication Engineers, pp. 69-114, Aug., 1987.
N. Tamba et al., "An 8ns 256K Bi CMOS RAM", 1988 IEEE International Solid State Circuits Conference, pp. 184-185, Feb. 18, 1988.
T. Yamanaka et al., "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Error Immunity", IEDM 88, pp. 48-51, 1988.
H. Shimada et al., "18 ns 1 Mbit CMOS SRAM", 1988 Conference of Electronics, Information & Communication Engineers, pp. 23-28, May 26, 1988.
A. Hirose et al., "1 Mbit CMOS SRAM", Mitsubishi Electronics Technical Report, vol. 62(6), pp. 81-84, Jun., 25, 1988.
T. Kamatsu et al., "35 ns 1 Mbit CMOS SRAM", 1987 Conference of Institute of Electronics, Information & Communication Engineers, pp. 43-48, Apr. 21, 1987.
"The Advent of 1M SRAM", Nikkei Microdevices, pp. 53-65, Mar. 1987.
T. Wada, et al "14 ns 1Mbit CMOS SRAM", 1988 Conference of Institute of Electronics, Information & Communication Engineers, pp. 29-35, May 26, 1988.

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