Wiring method in layout design of semiconductor integrated...

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout

Reexamination Certificate

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Reexamination Certificate

active

06727120

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a wiring method in layout design of a semiconductor integrated circuit, a semiconductor integrated circuit having a plurality of interconnection lines, and a functional macro.
FIG. 17
schematically illustrates a portion of interconnection lines of a semiconductor integrated circuit placed by a conventional general wiring method. Referring to
FIG. 17
, the reference numeral
10
(
0
) denotes a lower-order bit interconnection line for the 0-th bit as the least significant bit,
10
(
1
) a lower-order bit interconnection line for the first bit,
10
(
2
) a lower-order bit interconnection line for the second bit,
20
(
k
) a higher-order bit interconnection line for the k-th bit as the most significant bit,
20
(
k−
1) a higher-order bit interconnection line for the (k−1)th bit, and
20
(
k−
2) a higher-order bit interconnection line for the (k−2)th bit. These interconnection lines are placed in the ascending order from the least significant 0-th bit or the descending order from the most significant bit. The spacing between the adjacent interconnection lines is set constant. In this placement, the lower-order bits run side by side while the higher-order bits run side by side.
FIG. 19
illustrates a configuration of a functional macro
40
such as a memory to which the k+1 bit interconnection lines
20
(
k
) to
10
(
0
) described above are connected. The functional macro
40
has k+1 terminals
40
t
(k) to
40
t
(
0
) connected to the k+1 bit interconnection lines
20
(
k
) to
10
(
0
) placed in the ascending order from the 0-th bit as the least significant bit (or the descending order from the k-th bit as the most significant bit). Therefore, the terminals
40
t
(k) to
40
t
(
0
) are also placed in the ascending order from the 0-th bit as the least significant bit (or the descending order from the k-th bit as the most significant bit). The k+1 terminals
40
t
(k) to
40
t
(
0
) as a whole transmit or receive information as one unit of data or one address.
FIG. 18
is a diagrammatic illustration of a capacitance between interconnection lines. When two interconnection lines
1
and
2
running in parallel with each other are assumed, a parasitic capacitance is inevitably generated between the two interconnection lines, which is herein called a wiring capacitance
3
. When a digital signal on one of two interconnection lines changes from 0 to 1 while a digital signal on the other interconnection line changes in reverse, that is, from 1 to 0, it is called that these signals change to opposite phases. In the parallel interconnection lines
1
and
2
located close to each other, if the signals on these interconnection lines change to opposite phases, they both draw a charge existing in the parasitic capacitance (wiring capacitance
3
) formed therebetween. This increases delay in signal propagation.
Semiconductor micro-fabrication technology has advanced at rapid paces. In the level of fine technology before attainment of 0.5 &mgr;m, the spacing between interconnection lines was large enough to only generate a small value of parasitic capacitance, and thus there was no occurrence of the problem of increase in signal delay described above. However, at attainment of the level as fine as about 0.35 &mgr;m and then about 0.25 &mgr;m, this problem began to arise locally in interconnections for high-speed propagation. After attainment of the level of 0.18 &mgr;m, this problem has become more significant every time the process is updated. In addition, since it is difficult to correctly grasp what operation the wiring capacitance causes, there has even occurred an unexpected design problem in some cases.
Conventionally, for solving the problem of increase in signal delay, the following techniques, for example, are employed when high-speed operation is required: setting a rule to secure a large spacing between adjacent interconnection lines; providing an additional shield line between adjacent interconnection lines; and twisting (intersecting) interconnection lines.
However, in any of the above techniques of securing a large spacing between interconnection lines, providing a shield line, and twisting interconnection lines, the problem is solved at the expense of increase in the area of the semiconductor integrated circuit. Moreover, when interconnection lines both on which a signal frequently changes (that is, high in signal change frequency) are placed in parallel with each other, the probability that both signals change to opposite phases simultaneously is high. In the conventional wiring method shown in
FIG. 17
, the lower-order bits tend to be higher in signal change frequency compared with the higher-order bits. Therefore, when interconnection lines for lower-order bits are placed in parallel close to each other as in the configuration shown in
FIG. 17
, there is significantly high probability that delay in signal propagation may increase due to simultaneous change of signals to opposite phases and this may cause a problem in operation of the semiconductor integrated circuit.
SUMMARY OF THE INVENTION
An object of the present invention is providing a wiring method in layout design of a semiconductor integrated circuit having a plurality of interconnection lines, capable of effectively suppressing delay in signal propagation due to signal interference between the plurality of parallel interconnection lines while minimizing increase in area, and a semiconductor integrated circuit and a functional macro capable of effectively suppressing interference between signals described above.
To attain the above object, according to the present invention, attention is paid to the fact that when a plurality of interconnection lines are provided, signals propagating through the interconnection lines are different in signal change frequency, in particular, in multi-bit interconnection lines, signal lines for higher-order bits are considerably low in signal change frequency compared with signal lines for lower-order bits. In view of this fact, these interconnection lines, as well as a plurality of terminals of a functional macro connected to these interconnection lines, may be suitably placed based on the change frequency of the signals propagating through these interconnection lines. By this placement, interference between the signals can be effectively suppressed.
The wiring method in layout design of a semiconductor integrated circuit of the present invention is a method for placing interconnection lines for a plurality of bits in parallel two-dimensionally or three-dimensionally in layout design of a semiconductor integrated circuit, wherein the interconnection lines for a plurality of bits are placed in an ascending or descending order of the bits, interconnection lines for bits of ordinal numbers equal to or more than a predetermined ordinal number are placed adjacent to each other at a predetermined spacing, and interconnection lines for bits of ordinal numbers less than the predetermined ordinal number are placed adjacent to each other at a spacing exceeding the predetermined spacing.
Alternatively, the wiring method in layout design of a semiconductor integrated circuit of the present invention is a method for placing interconnection lines in parallel two-dimensionally or three-dimensionally in layout design of a semiconductor integrated circuit, wherein a signal change frequency at which a signal propagating through an interconnection line changes per unit time is determined for each of the plurality of interconnection lines by estimation or simulation, and the plurality of interconnection lines are placed based on the signal change frequency so that interconnection lines having a high signal change frequency and interconnection lines having a low signal change frequency are adjacent to each other.
In the method described above, in the case of transmitting a signal of a plurality of bits via the plurality of interconnection lines, the plurality of interconnection lines may be placed bas

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