Wiring method for semiconductor integrated circuits

Details Wiring method for semiconductor integrated circuits Wiring method for semiconductor integrated circuits

1992-01-31

1993-05-18

Thomas, Tom

Fishing, trapping, and vermin destroying

437195, 257499, H01L 2170

Patent

active

052121070

ABSTRACT:
A novel wiring method for multilayered semiconductor integrated circuits is disclosed. For example, a semiconductor integrated circuit of a 6-layered wiring structure can be formed with a first layer covered with gates, a second layer, a third layer, a fourth layer and a fifth layer making up logic wiring layers, and a sixth layer making up a power layer. Lattice-shaped wires are formed in a longitudinal direction on the second layer and the fourth layer, and in a lateral direction on the third layer and the fifth layer. The second layer forming the bottom layer and the fifth layer forming the uppermost layer, or a combination of the second layer and the fifth layer of a general wiring structure are used as main layers of wires requiring consideration of signal transmission delay time.

REFERENCES:
patent: 4516312 (1985-05-01), Tomita

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