Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1998-10-22
2001-01-23
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S115000, C438S116000
Reexamination Certificate
active
06177294
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring layout method for a semiconductor device in which a power supply wiring layer, a ground wiring layer, and an wiring layer for connecting elements to each other are formed by a plurality of wiring layers, and a recording medium on which a wiring layout program for the semiconductor device is recorded.
2. Description of the Related Art
As a conventional wiring layout method for a semiconductor device, for example, a layout method which sets a pattern shape and a wiring arrangement such that an area where a power supply wiring and a ground wiring oppose is made as large as possible is used (Japanese Patent Application Laid-Open No. 1-239964, Japanese Patent Application Laid-Open No. 5-055380, and the like). The wiring layout method described in Japanese Patent Application Laid-Open No. 1-239964 is called the first prior art, and the semiconductor integrated circuit device described in Japanese Patent Application Laid-Open No. 5-055380 is called the second prior art.
FIG. 1A
is a plan view showing the wiring of a semiconductor device in which the wiring is laid out by the wiring layout method according to the first prior art, and
FIG. 1B
is a sectional view of the wiring in FIG.
1
A. Here, as shown in
FIGS. 1A and 1B
, a wiring layer
55
connecting elements to each other, a ground wiring layer
52
, and a power supply wiring layer
53
for on a silicon substrate
51
are laminated. An interlayer insulator
54
a
is formed between the wiring layer
55
and the ground wiring layer
52
, and an interlayer insulator
54
b
is formed between the ground wiring layer
52
and the power supply wiring layer
53
. Power is supplied to an integrated circuit on the substrate
51
by the power supply wiring layer
53
and the ground wiring layer
52
through the interlayer insulators
54
a
and
54
b
. The power supply wiring layer
53
and the ground wiring layer
52
formed to oppose through the interlayer insulator
54
b
constitute a counter electrode of a wiring capacitor.
In the first prior art constructed as described above, a wiring capacitor is formed by using the interlayer insulator
54
b
, and a counter electrode is constituted by the power supply wiring layer
53
and the ground wiring layer
52
. When a bypass capacitor is formed between the power supply wiring layer
53
and the ground wiring layer
52
as described above, power supply noise or the like generated therebetween can be reduced.
FIG. 2A
is a plan view showing the wiring structure of a semiconductor integrated circuit device according to the second prior art, and
FIG. 2B
is a sectional view showing a part of the wiring structure in FIG.
2
A. Referring to FIG.
2
A, an insulating film
68
formed on the upper most layer in
FIG. 2B
is not illustrated. As shown in
FIGS. 2A and 2B
, a plurality of diffusion layers
61
a
are selectively formed at the surface of a silicon substrate
61
, and terminals
61
b
and the like to which a power supply voltage and a ground potential are applied are formed on the silicon substrate
61
, thereby constituting a plurality of active elements. A plurality of interlayer insulators
65
a
and a plurality of signal wiring layers
62
are alternately laminated on the silicon substrate
61
.
In addition, the power supply wiring layer
63
to which a power supply voltage V
DD
is applied is formed on the interlayer insulator
65
a
, and the power supply wiring layer
63
is selectively connected to a plurality of pads
67
formed on the peripheral portions of the chip. A interlayer insulator
65
b
and a ground wiring layer
64
to which a ground potential V
SS
is applied are sequentially formed on the power supply wiring layer
63
. The ground wiring layer
64
is selectively connected to the pads
67
. The power supply and ground terminals
61
b
of the active elements are connected to the power supply wiring layer
63
through a connection via hole
66
a
formed in the interlayer insulator
65
a
and connected to the ground wiring layer
64
through a connection via hole
66
b
formed in the interlayer insulators
65
a
and
65
b.
In the second prior art constructed as described above, when a counter electrode of a wiring capacitor is constituted by the power supply wiring layer
63
and the ground wiring layer
64
, electromagnetic noise can be suppressed from being generated.
However, when the layout method according to the first prior art is used, it is considerably difficult to design the optimum shapes of the power supply wiring layer
63
and the ground wiring layer
64
. It may be impossible to perform arrangement of the elements and formation of wiring. In addition, when the arrangement region of elements and the formation region of wiring are excessively estimated, a counter area between the power supply wiring layer
63
and the ground wiring layer
64
decreases, and an effective wiring capacitor cannot be obtained. In order to design the optimum shapes of the power supply wiring layer
63
and the ground wiring layer
64
, error and trial are repeated a plurality of times. The development period of a semiconductor device extends, and development costs increase.
In the semiconductor integrated circuit device according to the second prior art, the number of days for manufacturing the device and manufacturing costs disadvantageously increase. This is because, in general, even in a semiconductor device obtained by forming two wiring layers, at least three, four, or more wiring layers are required to manufacture an integrated circuit device as shown in
FIGS. 2A and 2B
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a wiring layout method for a semiconductor device, which is capable of easily obtaining a highly reliable semiconductor device at low cost and a recording medium on which a wiring layout program for the semiconductor device are recorded.
The wiring layout method for a semiconductor device according to the present invention comprises the step of determining a chip area and a chip region. Elements are arranged in the chip region, and a wiring for connecting the elements to each other is formed. The shapes of a power supply wiring layer and a ground wiring layer connected to the elements and oppositely arranged to be spaced apart from each other in the direction of the thickness of the chip are determined. The power supply wiring layer and the ground wiring layer are designed such that the counter area between these layers is made as large as possible.
The wiring layout method for a semiconductor device according to the present invention can comprise the step of estimating the number of elements formed in the chip region, an element area, a formation region of a wiring for connecting the elements to each other, and the minimum necessary formation region of the power supply wiring layer and the ground wiring layer, before the step of determining the chip area and the chip region. The chip area and the chip region are preferably determined on the basis of the number of elements, the element area, the formation region of the wiring, and the formation region of the power supply wiring layer and the ground wiring layer.
The wiring layout method for a semiconductor device according to the present invention preferably comprises the steps of temporarily arranging the elements in the chip region and laying out the power supply wiring layer and the ground wiring layer in the minimum necessary formation region, between the step of determining the chip area and the step of arranging elements in the chip region. In the step of arranging the elements, the arrangement positions of the elements can be determined on the basis of net list information used when a circuit of the semiconductor device is designed.
The wiring layout method for a semiconductor device according to the present invention preferably comprises the step of checking whether there are an element which is not arranged and a wiring which is not formed, between the step of arranging
Elms Richard
Lebentritt Michael
NEC Corporation
Scully Scott Murphy & Presser
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