Wiring-inclusive structure and forming method thereof

Details Wiring-inclusive structure and forming method thereof Wiring-inclusive structure and forming method thereof

2002-10-25

2004-08-24

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S210000, C257S759000, C257S760000

Reexamination Certificate

active

06781237

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2002-060774, filed on Mar. 6, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring-inclusive structure in which a wiring trench formed in an insulation film is filled with a conductive material having an easily diffusible property, especially, a Cu-containing metal material.
2. Description of the Related Art
As a semiconductor element becomes highly integrated and a chip size becomes smaller, microscopic formation of a wiring and a multilayered structure of wirings are acceleratedly promoted. In a logic device having such a multilayered wiring-inclusive structure, wiring delay is becoming one of dominant factors of signal delay of the device. The signal delay of the device is proportional to the product of a wiring resistance by a wiring capacity, and therefore, reduction in the wiring resistance and the wiring capacity is important to remedy the wiring delay.
In order to reduce this wiring resistance, it is being considered to form a wiring, using Cu which is a low resistant metal as its material. Here, since it is very difficult to form the wiring by patterning Cu, a so-called damascene method has been devised. In this damascene method, a wiring trench is formed in an insulation film and this wiring trench is filled with Cu to form the wiring. In the case when this damascene method is adopted, it is suitable to use a material with a low dielectric constant instead of conventionally used SiO
2
as the aforesaid insulation film in order to further reduce the wiring capacity.
As described above, Cu is highly prospective as a future wiring material since it is a low resistant metal, but on the other hand, it has a disadvantage of having an easily diffusible property to a generally used insulation material. Therefore, in a Cu wiring forming process by the damascene method, an SiN film having a function of Cu diffusion prevention and a function as an etching stopper is formed on a Cu wiring after the Cu wiring is formed in such a manner that Cu deposited on the insulation film is polished and removed by a CMP (Chemical Mechanical Polishing) method and it fills only the wiring trench in the insulation film.
However, since SiN has a relatively large dielectric constant of 7.0, a serious problem occurs that, even when a film with a low dielectric constant is used as the insulation film, the decrease in its dielectric constant is hindered by a fringe effect of SiN and an effective dielectric constant is not reduced.
SUMMARY OF THE INVENTION
The present invention is made in view of the above problem. It is an object of the present invention to suppress wiring delay and greatly reduce an effective dielectric constant of an insulation film in which the wiring is filled and formed, at the time of forming the wiring of a conductive material having an easily diffusible property to the insulation film, which is represented by Cu, by a damascene method and to thereby provide a highly reliable wiring-inclusive structure and a forming method thereof which respond to further microscopic formation of a semiconductor element in the near future.
As a result of assiduous studies, the inventor of the present invention has come up with various forms of the inventions described below.
A wiring-inclusive structure of the present invention is a wiring-inclusive structure which is so constituted that a wiring-shaped trench is formed in an insulation film provided above a substrate and the trench is filled with a conductive material having an easily diffusible property to the insulation film to form a wiring. Further, a diffusion preventive film which uses hydrogenated SiC as its material and whose film density is 2.1 (g/cm
3
) or higher is provided to cover an upper surface of the wiring.
Another form of a wiring-inclusive structure of the present invention is a wiring-inclusive structure which is so constituted that a wiring-shaped trench is formed in an insulation film provided above a substrate and the trench is filled with a conductive material having an easily diffusible property to the insulation film to form a wiring. Further, a diffusion preventive film which uses hydrogenated SiC as its material and contains 8 (atm %) to 20 (atm %) of N atoms is provided to cover an upper surface of the wiring.
A forming method of a wiring-inclusive structure of the present invention comprises the steps of: forming at least a wiring-shaped trench in an insulation film; filling the trench with a conductive material having an easily diffusible property at least to the insulation film to form a wiring; and forming a diffusion preventive film which uses hydrogenated SiC as its material to cover an upper surface of the wiring and to have a film density of 2.1 (g/cm
3
) or higher.
Another form of a forming method of a wiring-inclusive structure of the present invention comprises the steps of: forming at least a wiring-shaped trench in an insulation film; filling the trench with a conductive material having an easily diffusible property at least to the insulation film to form a wiring; and forming a diffusion preventive film which uses hydrogenated SiC as its material to cover an upper surface of the wiring. In this forming method, an N-containing gas is added into the diffusion preventive film in the step of forming the diffusion preventive film, and an N concentration in the diffusion preventive film is controlled to be 8 (atm %) to 20 (atm %).


REFERENCES:
patent: 6331481 (2001-12-01), Stamper et al.
patent: 6492734 (2002-12-01), Watanabe
patent: 6577011 (2003-06-01), Buchwalter et al.
patent: 6614096 (2003-09-01), Kojima et al.
patent: 2001/0030369 (2001-10-01), MacNeil et al.
patent: 2002/0020919 (2002-02-01), Li et al.
patent: 2002/0158337 (2002-10-01), Babich et al.
patent: 2002/0175415 (2002-11-01), Matsunaga
Patent Abstracts of Japan Publication No. 2001-244337 dated Sep. 7, 2001 Corresponds to U.S. patent application Publication No. 2001/0030369 A1.

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