Wiring for semiconductor device

Details Wiring for semiconductor device Wiring for semiconductor device

2001-06-20

2002-12-17

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S377000, C257S385000, C438S652000

Reexamination Certificate

active

06495920

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to wiring for a semiconductor device, and more particularly to wiring for a semiconductor device which is suitable for high density device packing, and a method for forming the same.
BACKGROUND OF THE INVENTION
In general, a conventional electrical connection wiring for a contact in a semiconductor device is produced by: forming an insulating film of a CVD oxide on a substrate having a semiconductor device formed thereon; forming holes in source/drain impurity regions; forming a titanium layer thereon for lowering contact resistance to the source/drain impurity regions; forming a TiN or Ti/W film as a diffusion prevention film; and forming an aluminum layer for electrical interconnection between cells. However, as semiconductor device packing advances, the size of chip has been reduced with consequential reductions in contact hole size. This has worsened the step coverage problems associated with the contact hole because the aspect ratio has increased as the hole has become smaller. An improved method for forming device wiring is needed.
Conventional wiring and a method for forming the wiring will be explained with reference to the attached drawings.
FIG. 1
illustrates conventional wiring for a semiconductor device, and
FIGS. 2
a
-
2
d
are cross-sections showing the steps of a conventional method for forming the wiring.
Referring to
FIG. 1
, the conventional wiring includes: a field oxide film
2
formed on a first conductive type semiconductor substrate (a P-type semiconductor substrate)
1
; a gate electrode
4
formed on the P-type semiconductor substrate
1
insulated from surroundings; source/drain regions
8
of LDD structures formed on the substrate on both sides of the gate electrode
4
; a CVD oxide film
9
and a planar protection film
10
in contact with a source/drain region
8
; a TiN layer
12
formed on a titanium layer
11
; an aluminum layer
13
formed on the TiN layer
12
; and a silicide region
11
a
formed under a portion of the titanium layer
11
in contact with the source/drain regions
8
on one side of the gate electrode
4
.
FIGS. 2
a
-
2
d
illustrate sections showing the steps of a conventional method for forming the wiring.
Referring to
FIG. 2
a,
a first pad oxide film and a nitride film are deposited in succession on a P-type semiconductor substrate
1
and a photoresist film is coated thereon and subjected to exposure and development for selective patterning. Using the patterned photoresist film as a mask, the nitride film and the oxide film are removed in succession (not shown). A field oxide film
2
is formed by thermal oxidation, and the photoresist film is removed. By way of thermal oxidation or chemical vapor deposition (CVD), an oxide film is deposited on the exposed surfaces and a silicon oxide film is deposited on the first polysilicon layer by a chemical vapor deposition. A photoresist film is coated thereon and subjected to exposure and development so as to pattern the photoresist and leave only a portion at which a gate electrode
4
is to be formed. Using the patterned photoresist film as a mask, the silicon oxide film and the first polysilicon layer are subjected to anisotropic etching successively to form a gate electrode
4
and a gate cap oxide film
5
.
After the gate electrode
4
and the gate cap
5
have been formed, phosphorus ions are injected into the P-type semiconductor substrate
1
on both sides of the gate electrode
4
at an ion injection energy of 30 KeV and dosage of abut 2.3×10
13
atoms/cm
2
to form lightly doped source/drain regions
6
. By way of thermal oxidation or chemical vapor deposition, a silicon oxide film is deposited and anisotropically etched to form sidewall oxide films
7
at sides of the gate electrode
4
and the gate cap oxide film
5
. Then, arsenic ions are injected into the P-type semiconductor substrate
1
aside the sidewall oxide films at an ion injection energy of 7 at 40 KeV and dosage of about 4.0×10
15
atoms/cm
2
to form highly doped source/drain regions
8
.
Referring to
FIG. 2
b,
the gate oxide film
3
on one side of the gate electrode
4
is removed. An undoped thin chemical vapor deposition oxide film
9
is formed on the exposed surfaces to a thickness of 1000 Å and a planar protection film (BPSG)
10
is formed on the film
9
to a thickness of 5000 Å and heat treated at an elevated temperature of 800-900° C. to make the surface planar. A photoresist film is coated and subjected to photolithography and development to pattern the photoresist film selectively.
Referring to
FIG. 2
c,
the exposed planar protection film
10
and the undoped CVD oxide film
9
are removed by reactive ion etching to expose the source/drain impurity regions
8
, after which the photoresist film is removed.
Referring to
FIG. 2
d,
a titanium layer
11
of about 1000 Å in thickness is sputtered on the entire surface for lowering the contact resistance, a TiN layer
12
of about 500 Å in thickness is sputtered thereon to serve as a buffer for the titanium layer and aluminum, and an aluminum layer
13
of the about 7000 Å in thickness is also sputtered thereon. A photoresist film is coated and subjected to photolithography and development so as to pattern the photoresist film selectively, i.e., only leave a portion under which wiring is to be formed. Using the pattered photoresist film as a mask, the exposed aluminum layer
13
and TiN layer
13
are removed in succession, and subjected to heat treatment for lowering resistance of the wiring, which results in formation of a silicide
11
a
under the titanium layer
11
in contact with the source/drain impurity region
8
.
The aforementioned wiring for a semiconductor device has the following problems.
First, the formation of the titanium layer, TiN layer and aluminum layer by sputtering (which produces high velocity ions of random direction) causes inferior step-coverage in the contact hole and, therefore, low reliability of the wiring.
Second, the etching of the thick insulating film on the semiconductor substrate at a shallow junction for formation of the contact hole may damage the semiconductor substrate including the source/drain regions.
Third, the implantation of etching gas into the semiconductor substrate during the formation of the contact hole increases a contact resistance between the semiconductor substrate and the wiring.
Fourth, as device packing density increases, the aspect ratio of the contact hole increases and the alignment tolerance between the gate structure and the contact hole for the bit line decreases (due to a size reduction in, and greater step of, the contact hole) which increases misalignment between the contact hole and the wiring making the wiring susceptible to a short with the gate electrode or the semiconductor substrate.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to wiring for a semiconductor device and a method for forming the same that substantially obviates one or more of the problems due to limitations and advantages of the related art.
These and other advantages in accordance with the purposes of the present invention are achieved by providing wiring for a semiconductor device that includes: impurity regions formed in a substrate on both sides of an insulated gate electrode; a first conductive layer formed on each of the impurity regions; and a second conductive layer in contact on one side of the gate electrode with the first conductive layer.
In another aspect of the present invention, a method is provided for forming wiring for a semiconductor device that includes the steps of: forming impurity regions in a substrate on both sides of an insulated gate electrode; and forming a second conductive layer in contact on one side of the electrode with the first conductive layer.
The foregoing and other objectives of the present invention will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and speci

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