Wiring design for semiconductor integrated circuit

Details Wiring design for semiconductor integrated circuit Wiring design for semiconductor integrated circuit

1988-12-21

1991-09-03

Lall, Parshotam S.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

050460170

ABSTRACT:
A method of designing semiconductor integrated circuits wherein rough routes are designated after a process of design for cells layout is completed, then wirings between cells are supposed automatically on the basis of the designated rough routes, investigation of the characteristic of the wirings is executed, and after a target characteristic is attained, a wiring pattern satisfying all of required electrical and physical conditions, including layout rules, i.e. a detailed wiring pattern, is prepared.

REFERENCES:
patent: 4754408 (1988-06-01), Carpenter et al.
patent: 4777606 (1988-10-01), Fournier
"LAS: Layout Pattern Analysis System with New Approach", by Y. Okamura et al., 1982 IEEE, pp. 308-311.
"EXCL: A Circuit Extractor for IC Designs", by S. P. McCormick, 21st Design Automation Conf., IEEE 1984, pp. 616-623.
"Resistance Extraction in a Hierarchical IC Artwork Verification System", by S. Mori et al., IEEE 1985, pp. 196-198.
"PANAMAP-B: A Mask Verification System for Bipolar IC", by J. Yoshida et al., 18th Design Automation Conf., IEEE 1981, pp. 690-695.

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