Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-02-24
2002-10-22
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C257S690000, C361S772000
Reexamination Certificate
active
06469260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring board. More particularly, the present invention relates to a wiring board ensuring a high reliability in connection and packaging and capable of preventing crosstalk between the adjacent wirings, and to a process for the production of the wiring board. The present invention also relates to a semiconductor device using the wiring board of the present invention and a process for the production thereof.
2. Description of the Related Art
Recently, there is a tendency that semiconductor elements (hereinafter, also referred to as “semiconductor chips”) to be packaged in semiconductor devices have an increased number of electrode terminals, because the functions of the semiconductor devices is increasing and widened with time. Further, to satisfy such a tendency, there has been used a method of forming electrode terminals in the form of an area array on an electrode terminal-providing surface of the semiconductor chip, followed by packaging the semiconductor chip on a wiring board by flip chip bonding. Using flip chip bonding, because the bumps formed on the electrode terminals of the semiconductor chip are bonded to the corresponding terminals (bumps) for external connection of the wiring board, it becomes possible to electrically connect the electrode terminals with the terminals for external connection. Furthermore, as a more recent tendency, there has been used a so-called “built-up method”, that is, a method of combining several plies of wiring board to form a laminated board. This method is particularly useful in the formation of fine wiring patterns, because the above-mentioned flip chip bonding method is not suited for the formation of such fine wiring patterns in view of a large diameter of the bumps of about 130 to
150 &mgr;m
and a long distance (pitch) between the adjacent bumps of about 200 to 250 &mgr;m.
FIG. 1
is a cross-sectional view illustrating one example of the prior art semiconductor device. In the illustrated semiconductor device
50
, a wiring board
1
has a semiconductor chip
10
packaged thereon, and the semiconductor chip
10
has area array-like distributed electrode terminals (bumps)
3
on a bottom surface thereof. The wiring board
1
has a built-up layer
9
in both surfaces thereof, and the one surface not bearing the semiconductor chip
10
has terminals (bumps)
2
for external connection. The semiconductor chip
10
is electrically connected through its electrode terminals
3
to a wiring pattern (not shown) of the built-up layer
9
, and also through a via (not shown) of the wiring board
1
to the terminals
2
for external.connection. Further, although only two plies of the built-up layers
9
are shown in
FIG. 1
for the purpose of simplification of the explanation, two or more plies of the built-up layers
9
can be laminated to form a wiring pattern which is used to electrically connect the electrode terminals
3
of the semiconductor chip
10
with the terminals
2
of the wiring board
1
. Furthermore, the wiring board
1
and the semiconductor chip
10
packaged thereon are encapsulated with an electrically insulating resinous material
4
.
In the semiconductor devices such as those shown in
FIG. 1
, the built-up layer is generally produced by using an electrically insulating resinous material such as epoxy resin or polyimide resin as a substrate. After a predetermined wiring pattern was formed on a surface of the substrate to form a built-up layer, a required number of the built-up layers (pattern-bearing substrates) are laminated, while the wiring patterns are electrically connected between the built-up layers. The resulting semiconductor devices are suitable for the formation of highly dense wiring pattern because of their built-up structure. However, they suffer from a troublesome and complicated production process and thus a highly increased production cost. In addition to these drawbacks, the semiconductor devices have a problem that reliability and production efficiency, i.e., yield, of the devices are reduced because crosstalk arises in the devices due to the short distance between the wiring patterns.
To solve the above-mentioned problems of the prior art semiconductor devices, the present inventors have developed a semiconductor device disclosed in Japanese Unexamined Patent Publication (Kokai) No. 11-163217. As shown in
FIG. 2
, the semiconductor device
50
comprises a wiring board
1
having packaged thereon a semiconductor chip
10
. The semiconductor chip
10
has electrode terminals (not shown) provided in the pattern of area array on a lower surface thereof. The semiconductor chip
10
is packaged on one surface of the wiring board
1
in such a manner that the electrode terminals-bearing surface of the semiconductor chip
10
is outwardly positioned. Further, the same surface of the wiring board
1
has bonding pads
5
which are distributed in the form of an area array except for the chip packaging area thereof. The electrode terminal of the semiconductor chip
10
and the bonding pad
5
are electrically connected through a bonding wire
6
comprising a conductor wire and an insulating layer surrounding the wire. Furthermore, in another surface of the wiring board
1
, i.e., in the surface having no semiconductor chip of the wiring board
1
, the bonding pad
5
having a pattern of area array and terminal
2
for external connection are electrically connected through a conductor section
7
. As is shown, the conductor section
7
is passed through the wiring board
1
in a direction of the thickness thereof. The connection between the conductor section
7
and the terminal
2
is made through a land
12
formed on an end surface of the conductor section
7
. Moreover, a connection section between the electrode terminal and the bonding wire
6
and a bonding section between the bonding wire
6
and the bonding pad
5
including an adjacent area to these sections are coated with an electrically insulating layer
8
and also the chip side surface of the wiring board
1
including the semiconductor chip
10
and the bonding wires
6
is encapsulated with an electrically conductive resinous material
11
.
Using the semiconductor device
50
illustrated in
FIG. 2
, since the electrode terminals of the semiconductor chip
10
and the bonding pads
5
of the wiring board
1
are connected through an insulating layer-coated bonding wire
6
, it becomes possible to simplify the constitution of the wiring board, thereby ensuring easy production and high yield of the semiconductor devices. In addition, since the wiring necessary to complete the semiconductor device can be shortened, it becomes possible to provide semiconductor devices having excellent electric properties.
However, the above-discussed and other prior art semiconductor devices are insufficient to fully satisfy the various requirements for the semiconductor devices. It is therefore desired to further improve the prior art semiconductor devices. More particularly, for the semiconductor device of
FIG. 2
, since the wire bonding method is used in the connection between the terminals, the bonding operation may adversely affect the semiconductor chip and its properties. For example, heat applied to the bonding wires during bonding may cause damage to the semiconductor chip. Further, with regard to the configuration of the wiring boards, from the view point of the producers of semiconductor devices, the wiring boards provided by their makers are desired to be supplied to the device producers as products having configurations capable of easily packaging semiconductor chips.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a wiring board which exhibits a high reliability of electrical connection in the board and a high reliability of packaging of semiconductor and other chips, can prevent crosstalk between the adjacent wirings, has an excellent heat dissipation property, can easily produce impedance matching in the board, can be prod
Horiuchi Michio
Kurihara Takashi
Paul & Paul
Shinko Electric Industries Co. Ltd.
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