Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-10-15
2002-03-05
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S258000, C174S259000, C174S262000, C174S264000, C361S792000, C029S830000, C029S852000
Reexamination Certificate
active
06353189
ABSTRACT:
TECHNICAL FIELD
The present invention relates to wiring boards that have a plurality of wiring layers, and in particular to wiring boards that have less electromagnetic interference. Further, the present invention relates to wiring boards that are excellent in productivity and have a structure appropriate for packaging of high density.
In addition, the present invention relates to a fabrication method of the wiring boards, and in particular to a fabrication method of the wiring boards capable of fabricating wiring boards adequate for packaging of high density with high productivity.
Further, the present invention relates to semiconductor packages, and in particular to semiconductor packages that are less in electromagnetic interference. Still further, the present invention relates to semiconductor packages that can mount a semiconductor element of high degree of integration.
BACKGROUND ART
In recent years, high functionality of wiring boards is in progress. This is because when mounting a semiconductor device such as a semiconductor element or the like on a wiring board, corresponding to demand for high functionality and high integration of a semiconductor device, demand for high integration and high functionality at system level occurs. In order to package such a semiconductor device, there is a necessity to give a wiring board various functions. For instance, corresponding to high densification and multiple pinning of the semiconductor device itself, fine patterning of pitches connecting between a semiconductor device and a wiring board mounting thereof, and fine patterning of wiring pitches (L/S) of the wiring board itself are in demand.
A conventional printed wiring board, due to its fabrication method, has a disadvantage that its wiring area becomes smaller due to through holes disposed for interlayer connection. This is because when through holes for interlayer connection are formed, a layer other than necessary one is also bored. Thus bored holes make less the wiring area for the other wiring layers. To solve such problems, there has been proposed a wiring board in which only the layers necessary for interlayer connection can be selectively bored.
As one of such wiring boards, there is an IVH board in which multiplication of layers is accomplished by stacking boards of which interlayer connection is formed by the use of through holes as identical as the conventional wiring board. For such an IVH board, each layer requires a step of boring, in addition after stacking them a step of further boring is necessary, thus resulting in an extremely expensive wiring board. In such type wiring board in which interlayer connection is furnished by the use of through holes, there was a problem that due to plating a thickness of conductor of a wiring layer becomes thick accordingly it is difficult to obtain fine patterning of wiring. On the other hand, there has been proposed another type of wiring boards in which pillars (protruded electrode) are formed on a wiring layer by the use of conductive resin, and interlayer connection of a plurality of wiring layers is furnished by letting the conductive pillars pierce through a prepreg.
In these wiring boards, compared with the conventional wiring boards, the steps of boring, plating and polishing are made unnecessary for furnishing interlayer connection, and only necessary portions can be furnished with interlayer connections. Accordingly, in addition to improvement the degree of freedom of design, productivity can be improved.
Further, compared with connection with through holes, interlayer connection can be implemented without decreasing an area that can package electronic parts. In addition, since the plating is unnecessary, thickening of a wiring layer can be avoided, and fine patterning of wiring can be implemented easily.
However, in such type wiring boards in which interlayer connection is implemented by the use of the conductive pillars, there were following problems.
First, when with a wiring board that has multiple layers furnished by the use of conductive pillars as a core material further wiring layers are stacked on the outside thereof, there is a problem that reliability of the wiring boards is difficult to maintain. The conductive pillars that are formed by the use of conductive paste are such hard as to pierce through a prepreg. Accordingly, there was a problem that via lands and conductive pillars at portions of interlayer connection of the core material are tend to deform. According to the observation of the inventors, this is because that since insulating layers of the core material and external layer material are composed of approximately identical materials, due to heating during a step of stacking the layer of insulating resin constituting the core material softens to deform due to pressure during the step of stacking. When such deformation occurs, reliability of interlayer connection is deteriorated. Accordingly, conditions in the step of stacking such as temperature, pressure or the like are required to control rigorously, resulting in restricting productivity.
Further, so far, there was another problem that the conductive pillars disposed on base material and core material, because the thickness of insulating layers is thick, tend to be broad in diameter. When a diameter is made small, there is a case where sufficiently reliable interlayer connection due to the conductive pillars can not be obtained. In order to secure reliability of connection, process conditions must be rigorously controlled.
The present invention is made out to solve such problems as described above.
That is to say, an object of the present invention is to provide wiring boards having a structure that in addition to being able to cope with packaging of high density, is high in productivity and reliability.
Further, another object of the present invention is to provide a fabrication method of wiring boards having a structure that in addition to being able to cope with high density packaging, is high in productivity and reliability.
Still another object of the present invention is to provide semiconductor packages that are capable of packaging a semiconductor element of high degree of integration and of high operating speed.
Now, as electronic instruments become smaller, for instance smaller high frequency oscillators are in demand. To cope with such a demand, in oscillators of high frequency, dielectric boards thereon signal lines (strip lines) are formed are stacked, on this multi-layered wiring board, other than the signal lines, other wiring pattern is disposed, and various kinds of electronic parts are mounted.
Further, when transmission lines are disposed on a surface of a stacked dielectric board and other wiring pattern is formed within the stacked dielectric board (disposed inside) signal radiation is generated to be likely to adversely affect on the other wiring pattern. In addition, external electromagnetic noise may adversely affect to induce malfunction of wiring circuits including transmission lines, semiconductor packages, and electronic instruments.
To cope with such problems, as essential configurations are shown with sections in FIG.
26
and
FIG. 27
, respectively, there is a trial in which while a pair of ground layers
92
a
and
92
b
sandwich a transmission line
91
or a via hole
99
from up and down directions, further on the sides of both side surfaces of a transmission line
91
or a via hole
99
, shield patterns
93
a
and
93
b
(one turn type) are disposed to electrically connect to the ground layers
92
a
and
92
b.
That is, by constituting so as to surround a transmission line
91
from up and down directions and right and left directions, the transmission line
91
is secured in shielding (Japanese Patent Laid-open Publication No. Hei 5-299878). Incidentally, in FIG.
26
and
FIG. 27
, reference numeral
94
denotes a dielectric layer (insulating layer).
However, in the case of a shield structure such as described above being employed, ordinarily, although the thickness thereof is in the range of from sever
Fukuoka Yoshitaka
Sasaoka Kenji
Shimada Osamu
Takagi Akihiko
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Gaffin Jeffrey
Kabushiki Kaisha Toshiba
Patel I B
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