Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-12-19
2003-12-30
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S775000, C257S779000, C257S781000, C257S784000, C257S787000, C174S050510, C174S251000, C174S263000
Reexamination Certificate
active
06670718
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring board, a semiconductor device, and a process for the production of wiring boards, and particularly to an effective technology applied to a semiconductor device of LGA (Land Grid Array) type.
2. Prior Art
Heretofore, there has been a semiconductor device of CSP (Chip Scale Package) type wherein a ball-like bump (ball terminal) is connected as an external connection terminal for connecting the semiconductor device to a mount board such as a mother board, or an external device as the one wherein a semiconductor chip has been mounted on a wiring board.
The above-described semiconductor device of CSP type is arranged as shown in, for example,
FIGS. 1A and 1B
, in such that a wiring board in which an electric wiring
2
and an external connection terminal
2
A are disposed on a first principal plane (a side of the front) of an insulating substrate
1
such as a polyimide tape is placed, and a semiconductor chip
6
is mounted on the surface on which the electric wiring
2
of the wiring board (the insulating substrate
1
) has been formed in, for example, such a manner that its external electrode
601
is opposed to the above-described surface wherein the electric wiring
2
of the above-described wiring board is connected with the external electrode
601
through a protrusion conductor
13
.
FIG. 1B
is a sectional view taken along the line C-C′ of FIG.
1
A. Furthermore, a gap between the wiring board (insulating substrate
1
) and the semiconductor chip
6
is subjected to under-filling sealing by means of a sealing insulator
9
made of, for example, an epoxy-based thermosetting resin and the like in the above-described semiconductor device. Besides, an opening
101
for connecting a ball terminal is defined at a predetermined position of the insulating substrate
1
, for example, a site where, for example, the external connecting terminal
2
has been disposed, and it is guided to a second principal plane opposed to the first principal plane by means of a through hole plating
15
provided around the opening
101
or a conductive member filled inside the opening
101
. To the opening
101
, a ball terminal
16
made of, for example, a Pb—Sn based solder and the like is connected.
In case of the above-described semiconductor device of CSP type, however, when the ball terminal
16
of the semiconductor device of CSP type is connected with an electric wiring
11
of a mount board
10
such as a mother board to mount the semiconductor as shown in
FIG. 2
, a height t extending from a mounting surface
10
A of the above-described mount board
10
to the upper surface
6
A of the semiconductor chip
6
in the semiconductor device becomes higher by an amount corresponding to a height t′ of the above-described ball terminal
16
. For this reason, a container (casing) for containing the mount board
10
on which the above-described semiconductor device of CSP type has been mounted becomes thicker, so that it is difficult to reduce a size of the semiconductor device.
Moreover, since the external electrode
601
of the above-described semiconductor chip
6
is connected with the electric wiring
2
by means of the protrusion conductor
13
in the case when the semiconductor chip
6
is subjected to flip-chip junction on the wiring board, a distance (stand-off) extending from the insulating substrate
1
to a circuit-forming surface of the semiconductor chip
6
becomes higher, so that the semiconductor device becomes thicker, whereby it is difficult to thicken the same.
In this connection, there is a semiconductor of LGA type wherein an unrelieved external connecting terminal is disposed in place of the above-described ball terminal
16
as a manner for preventing from an appearance of a thicker semiconductor device. In the above-described semiconduct or device of LGA type, an electric wiring
2
is formed on a principal plane of an insulating substrate
1
, and an external connecting terminal (land)
17
is formed on a surface opposed to the surface on which the electric wiring of the above-described insulating substrate
1
has been formed as shown in FIG.
3
. In this case, the electric wiring
2
is electrically connected with the land
17
by means of a through-hole plating
15
provided around a via hole
102
defined on the above-described insulating substrate
1
. The outer periphery of the land
17
may be covered with a protective film such as a solder resist. In case of the above-described semiconductor device of LGA type, a plating layer
4
B prepared by laminating a nickel plating layer and a gold plating layer having good solderability on a surface of the land
17
. In this respect, a soldering paste or the like has been previously applied onto a predetermined position of the surface of the above-described land
17
or the electric wiring
11
on a mount board
10
, and then, the semiconductor device is mounted.
In case of such a semiconductor device of LGA type, since there is no ball terminal
16
as in a semiconductor device of CSP type, a height of the semiconductor device can be reduced in the case when it is mounted on the mount board
10
, whereby the present semiconductor device can be made thinner than that of the above-described semiconductor device of CSP type.
A wiring board used in the above-described semiconductor device of LGA type is prepared as described here in after. First, conductive thin films
18
made of a copper foil and the like are formed on both principal planes of an insulating substrate made of a polyimide tape and the like, the conductive thin film on a side of either principal plane is etched to form an external connection terminal
17
, and then, a via hole
102
is defined at a predetermined position of the above-described external connection terminal
17
by means of laser or the like as shown in FIG.
4
A.
Thereafter, a through-hole plating
15
is formed around the via hole
102
as shown in
FIG. 4B
, and an electric wiring
2
is formed from the conductive thin film
18
on the surface opposed to that on which the above-described external connection terminal
17
has been formed by the use of, for example, an additive plating method or the like method. In this occasion, a connection terminal
2
A, which is to be connected to a through-hole plating
15
in the above described via hole
102
, is formed on the electric wiring
2
.
Then, as shown in
FIG. 4C
, a plating layer
4
A prepared by laminating, for example, a nickel plating layer and a gold plating layer is formed on a surface of the above-described electric wiring
2
as well as a plating layer
4
B prepared by laminating, for example, a nickel plating layer and a gold plating layer is formed on a surface of the above-described external connection terminal
17
. A wiring board used for a semiconductor device of LGA type is obtained in accordance with the procedure as described above.
For instance, a semiconductor chip
6
is subjected to flip-chip mounting on a surface on which the electric wiring
2
of a wiring board prepared in accordance with the above-described procedure has been formed, and a liquid resin is poured in between the above-described wiring board (insulating substrate
1
) and the semiconductor chip
6
to complete under-filling sealing, whereby a semiconductor device of LGA type can be obtained as shown in FIG.
3
.
In a semiconductor device of CSP type shown in
FIG. 1
, however, it is required to maintain certain spacing in between the openings
101
so as not to be in contact with the ball terminals
16
each other. The same situation is observed in also the semiconductor device of LGA type shown in
FIG. 3
wherein it is required to maintain a certain spacing in between the via holes
102
so as not to be in contact with the external connection terminals (lands)
17
each other. In this respect, via holes
102
must be formed with a certain spacing from a constructional point of view in case of any of the semiconductor devices described above, other
Chinda Akira
Matsuura Akira
Chambliss Alonzo
Hitachi Cable Ltd.
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