Wiring board, manufacturing method thereof, semiconductor...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S758000

Reexamination Certificate

active

10910307

ABSTRACT:
The invention provides a wiring board having a small-scale and high-performance functional circuit while realizing a multi-layer wiring with a small number of steps. In addition, the invention provides a semiconductor device in which a display device is integrated with such high-performance functional circuit on the same substrate. According to the invention, first to third wirings, first and second interlayer insulating films and first and second contact holes are formed over a substrate having an insulating surface. The second wiring is wider than the first wiring, or the third wiring is wider than the first wiring or the second wiring. The second contact hole has a larger diameter than the first contact hole.

REFERENCES:
patent: 5330616 (1994-07-01), Yamazaki
patent: 5440138 (1995-08-01), Nishi
patent: 5508540 (1996-04-01), Ikeda et al.
patent: 5594569 (1997-01-01), Konuma et al.
patent: 5880497 (1999-03-01), Ikeda et al.
patent: 5940732 (1999-08-01), Zhang
patent: 6037197 (2000-03-01), Yamazaki et al.
patent: 6077731 (2000-06-01), Yamazaki et al.
patent: 6183937 (2001-02-01), Tsai et al.
patent: 6294815 (2001-09-01), Yamazaki et al.
patent: 6466303 (2002-10-01), Omura et al.
patent: 6468844 (2002-10-01), Yamazaki et al.
patent: 6504237 (2003-01-01), Noguchi et al.
patent: 6534242 (2003-03-01), Sugita et al.
patent: 6556264 (2003-04-01), Hirakata et al.
patent: 6558881 (2003-05-01), Tokushima
patent: 6734463 (2004-05-01), Ishikawa
patent: 6835971 (2004-12-01), Toyoshima et al.
patent: 6838698 (2005-01-01), Yamazaki et al.
patent: 6936847 (2005-08-01), Tanabe et al.
patent: 7009262 (2006-03-01), Isikawa
patent: 7053487 (2006-05-01), Saito et al.
patent: 2001/0052950 (2001-12-01), Yamazaki et al.
patent: 2002/0000551 (2002-01-01), Yamazaki et al.
patent: 2002/0030189 (2002-03-01), Ishikawa
patent: 2003/0080436 (2003-05-01), Ishikawa
patent: 2003/0193627 (2003-10-01), Hirakata et al.
patent: 2004/0256620 (2004-12-01), Yamazaki et al.
patent: 2006/0118888 (2006-06-01), Isikawa
patent: 1438703 (2003-08-01), None
patent: 06-268177 (1994-09-01), None
patent: 2001-142224 (2001-05-01), None
patent: 2003-203926 (2003-07-01), None
U.S. Appl. No. 09/649,845, filed Aug. 28, 2000 for Method of Fabricating Semiconductor Device, and Substrate Formed With Semiconductor Device (Katsumara et al.)-Specification, claims and drawings.
Qing Ma., “A four-point bending technique for studying subercritical growth in thin films and at interfaces”, J. Mater, Res., vol. 12, No. 3, Mar. 1997, pp. 840-845.
H. Ishiuchi et al., “Embedded DRAM Technologies”, 1997 IEDM IEEE, Section 2.3.1. pp. 33-36.
Chinese Office Action (Application No. 200410076687.3; CN7296) Dated Mar. 7, 2008 with Full English Translation.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Wiring board, manufacturing method thereof, semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wiring board, manufacturing method thereof, semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wiring board, manufacturing method thereof, semiconductor... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3922514

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.