Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2011-03-29
2011-03-29
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C029S847000, C029S852000, C174S258000, C174S260000, C174S262000, C257S736000, C257S737000, C257S738000, C257S739000, C257S777000, C257S778000, C257SE23069, C257SE21511, C257SE23062, C257SE29295, C257SE21505, C438S108000, C438S533000, C438S610000, C438S611000, C438S612000, C438S613000, C438S614000, C438S615000, C438S616000, C438S617000, C438S618000, C438S622000
Reexamination Certificate
active
07915088
ABSTRACT:
A semiconductor device100has such a structure that a semiconductor chip110is flip-chip mounted on a wiring board120. The wiring board120has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer122, a second layer124, a third layer126and a fourth layer128are provided. The first layer122has a first insulating layer121and a second insulating layer123. A protruded portion132which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad130is formed on a whole periphery over a boundary surface between the first insulating layer121and the second insulating layer123.
REFERENCES:
patent: 6418615 (2002-07-01), Rokugawa et al.
patent: 2004/0060174 (2004-04-01), Imafuji et al.
patent: 10-209163 (1998-10-01), None
patent: 2000-323613 (2000-11-01), None
Kaneko Kentaro
Kobayashi Kazuhiro
Nakamura Jun-ichi
Abdelaziez Yasser A
Garber Charles D
Rankin , Hill & Clark LLP
Shinko Electric Industries Co. Ltd.
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