Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-12-28
2001-03-20
Gandhi, Jaypprakash N. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S050510, C174S256000, C174S257000, C174S259000, C174S260000, C361S748000, C361S760000, C361S768000, C361S782000, C361S783000, C257S704000, C257S739000, C310S348000, C029S846000, C438S118000, C427S096400, C428S209000, C156S153000, C216S052000
Reexamination Certificate
active
06204454
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring board suitable for mounting electronic parts such as various chip elements and a process for the production thereof.
2. Background Art
Electronic hardware has been increasingly embodying lightness, thinness, compactness and smallness, and a resistor, a coil, a condenser and others such as a semiconductor, an SAW element, a sensor, etc., are formed as chips. And, recently, there are widely used surface mounting techniques of mounting chip elements directly on the surface of a wiring board like a COB (chip-on-board) structure.
A wiring board formed of a resin in particular is easily produced by molding and is excellently inexpensive, and such wiring boards are laminated and bonded to be used as a container for an electronic part. A wiring board and a container for an electronic part have come to be substantially not distinct from each other.
A conventional wiring board will be explained below.
FIG. 7
is a cross-sectional view of a conventional wiring board for showing a structure in which a pad on which a chip element is to mounted, i.e., a pad for connecting an electronic part, is formed on an upper surface. A conductor layer
102
formed of a copper foil and a copper plating layer coated on the copper foil is laminated on the upper surface of a substrate
101
formed of an epoxy resin or a BT resin, and a pad
104
on which a chip element
103
is to be mounted and bonded is formed on part of the upper surface of the conductor layer
102
. The entire upper surface of the conductor layer
102
, including that upper surface of the conductor layer
102
which is to constitute an under layer of the pad
104
, is a surface from which an oxide layer is removed and which is roughened with a scrubber, etc., so as to have a surface roughness of approximately 0.3 to 0.5 &mgr;m for easy bonding of a resin layer
106
such as a prepreg or a resist to the upper surface of the conductor layer
102
by an anchor effect.
A bump
108
of the chip element
103
is attached to the pad
104
, and the pad
104
and the bump
108
are electrically connected to each other by means of ultrasonic wave, an electrically conductive adhesive or soldering. The upper surface of the pad
104
is therefore required to be flat. Therefore, a nickel layer having a thickness of approximately 5 to 10 &mgr;m is laminated on the conductor layer
102
, and then, a metal layer having a thickness of 0.5 to 3 &mgr;m is stacked thereon, to constitute the pad
104
formed of a plurality of these plating layers.
In many cases, further, as shown in
FIG. 7
, the mounted chip element is sealed and protected by attaching and laminating an approximately 0.5 to 1.0 mm thick cover layer
107
formed of an epoxy resin or a BT resin on an upper surface of the conductor layer
102
. In this instance, the cover layer
107
is placed on the wiring board through the resin layer
106
, and it is laminated and bonded by heating under pressure. The resin layer
106
is a layer used for bonding by providing a bonding prepreg having a thickness of approximately 0.05 to 0.1 mm, heating the prepreg to allow it easily flow so that it flows over bonding surfaces, and applying a pressure to promote the flowability and fully adapt it to the bonding surfaces.
In some cases, an ink is used to print characters, symbols, etc., in the position of the above resin layer
106
.
For further accomplishing a lighter, thinner and smaller electronic machine or device, a wiring board is required which permits, for example, highly accurate face-down mounting on the scale of micron units, and it comes to be essential to make the occupation area of the pad on the wiring board as small as possible for attaining the high-density mounting of parts and the downsizing of the wiring board.
Concerning the above demand, the above prior art involves a problem that it is not possible to minimize the area of the pad to a necessary limit. When a structure member such as the cover layer is laminated on and bonded to the wiring board, an adhesive resin of a prepreg or an adhesive (resin layer) is softened under heat and pressurized for bonding, to flow over to an upper surface of the pad.
FIG. 8
is a cross-sectional view of an essential portion showing the flowing of a prepreg over onto an upper surface of the pad due to the softening of the prepreg under heat during bonding. On the clean and flat upper surface of the pad, the resin is easily spread, and a highly flowable component
106
a
contained in the resin is mostly transparent, so that the component
106
a
is difficult to recognize even if it is spread over the pad. Moreover, a film of the resin cured on the pad extremely impairs a bonding capability. Otherwise, when a chip element is already bonded, the above resin may flow onto the bump of the chip element or the chip element itself, and the functions thereof, i.e., the connecting function or the chip element characteristics may be inhibited. According to prior art, therefore, the pad is generally required to have greater dimensions than the chip element for reliable bonding to secure a resin-flow tab by taking account of safety, and the pad is required to be broader than necessary as compared with the size of the chip element, which has resulted in a large size of the wiring board. When the pad has a small size, the distance between the outer circumferential portion thereof, i.e., the outer circumference of the pad and the inner circumference of the resin layer is required to be sufficiently large in order to avoid the flowing of the component which flows out from the resin layer onto the bump of the chip element and the chip element itself, and as a result, it has been difficult to further downsize the wiring board.
Further, according to the prior art, the entire upper surface of the conductor layer is roughened by treatment with a scrubber like roughening by scraping with a wire brush. The above conventional roughened surface has a roughness which is not only non-uniform in depth but also is in the state of unidirectionally leaned scratches, and the roughened surface neither has necessarily good adhesion to the above resin layer such as a prepreg or an adhesive nor has sufficient capability of fitting to a cover, and the like.
Furthermore, the above directionally roughened surface formed by physical treatment exhibits the function of preventing the flow of a certain quantity of a resin in the direction at right angles with the direction in which grooves formed by the roughening extends, while it exhibits almost no function of preventing the flow of a resin in the direction in parallel with the direction in which the grooves extend.
In general, conventional wiring boards have a problem that they cannot comply with demands of the lightness, thinness, compactness and smallness of different electronic machines and devices.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a highly accurate wiring board suitable for mounting electronic parts in a high density by overcoming the problems which the above prior art has left unsolved.
It is another object of the present invention to provide a process for the production of a wiring board, which enables the production of micro-processed highly accurate wiring boards in simplified steps.
The above object is achieved by the present invention specified below.
(1) A wiring board having a conductor layer formed on a substrate and a connecting pad disposed in a connecting pad disposition portion provided in part of the conductor layer surface, a resin inflow prevention portion being provided adjacently to the said connecting pad disposition portion of the conductor layer, the resin inflow prevention portion having a surface roughness greater than the surface roughness of the said connecting pad disposition portion.
(2) A wiring board according to the above (1), wherein a resin layer formation portion is provided adjacently to the said resin inflow prevention portion of the conductor layer, and the resin la
Gotoh Masashi
Kanazawa Jitsuo
Yamamoto Syuichiro
Gandhi Jaypprakash N.
Oblon, Spivak, McClelland, Maier & Neustadt, P.C
TDK Corporation
Vigushin John B.
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