Wiring arrangement for a semiconductor device using insulating a

Details Wiring arrangement for a semiconductor device using insulating a Wiring arrangement for a semiconductor device using insulating a

1994-04-08

1995-03-07

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

257754, 257758, H01L 23485, H01L 2962

Patent

active

053960920

ABSTRACT:
An integrated circuit has an interconnection pattern which is recessed in the insulating layer, for example, an oxide layer. A groove is etched in the insulating layer corresponding to the metal pattern by means of a mask which is the inverted image of the interconnection pattern during manufacture. Etching is continued until contact windows are fully opened. To prevent the oxide between the contact windows also being removed, an etching stopper layer is provided in the oxide layer. A layer already present in the process may be used for this etching stopper layer, for example, a polycrystalline silicon layer, so that extra process steps are made redundant.

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patent: 4488166 (1984-12-01), Lehrer
patent: 4618878 (1986-10-01), Aoyama et al.
patent: 4728627 (1988-03-01), Mase et al.
patent: 4754311 (1988-06-01), Davids et al.
patent: 4808552 (1989-02-01), Anderson
IBMTDB, Low Sheet Resistance Gate Electrode with Conventional Borderless Contacts, vol. 32, No. 6B, Nov. 1989, pp. 122-123.
J. L. Yeh et al, IEEE Proc. VLSI MIC, pp. 95-100, 1988.

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