Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-01-30
2007-01-30
Deo, Duy-Vu N (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S720000
Reexamination Certificate
active
10099972
ABSTRACT:
The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained.
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Kusuyama Yoshihiro
Ono Koji
Suzawa Hideomi
Yamazaki Shunpei
Deo Duy-Vu N
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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