Wireless receiver deinterleaver having partitioned memory

Multiplex communications – Generalized orthogonal or special mathematical techniques – Particular set of orthogonal functions

Reexamination Certificate

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C375S130000

Reexamination Certificate

active

07440392

ABSTRACT:
A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with a prescribed subcarrier frequency. Each code word fragment includes a prescribed number of code word bits based on a prescribed modulation of the interleaved data stream, and the code word bits for each code word fragment are written into respective selected locations of the corresponding memory bank based on the prescribed modulation and the corresponding prescribed subcarrier frequency. The deinterleaver module outputs deinterleaved data from the memory banks based on parallel output of the respective stored code word bits from a selected address of the memory banks.

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Horvath et al., “A Novel, High-Speed, Reconfigurable Demapper—Symbol Deinterleaver Architecture For DVB-T”,Circuits and Systems, 1999, ISCAS '99, Proceedings of the 1999 IEEE International Symposium on Orlando, FL, USA May 30-Jun. 2, 1999, Paged 382-385.
IEEE Std. 802.11a-1999, “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5 GHZ Band”, L.AN/MAN Standards Committee of the IEEE Computer Society, IEEE-SA Standards Board, Approved Sep. 16, 1999, New York, USA.

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