Multiplex communications – Wide area network – Packet switching
Patent
1994-01-31
1995-12-12
Kizou, Hassan
Multiplex communications
Wide area network
Packet switching
370 854, 370 8511, 370 941, 379 58, 455 531, H04B 715, H04L 12403, H04L 1256
Patent
active
054756812
ABSTRACT:
An improved network interface architecture for a packet switch provides a mechanism for handling voice and data packets. Bandwidth allocation can be changed because control and data memories are synchronized to one another. A hierarchical addressing technique is employed to enhance flexibility in handling packet information. This method permits packet message data and certain packet control data to be stored in memory locations without having to be duplicated at a different memory location prior to transmission of the packet. In an exemplary wireless TDMA packet network a control module (CM) sends a time stamp relative to the beginning of its frame in a synchronization packet allowing each of a plurality of user modules (UM) to maintain synchronization relative to the CM. The CM uses a plurality of directional antennas and transmits the synchronization packets over each antenna over a predetermined number of frames. The UMs use a receive time stamp to identify the beginning of a received synchronization packet. The difference between the time stamps combined with a delay constant is used by the UMs to adjust time synchronization to the CM frame. Packets are communicated between the controller and the peripherals at the UM and CM over a bus using a communication protocol which increases the efficiencies of packet communications by allowing additional direct command lines between the communications controller and peripherals.
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Advanced Peripherals, IEEE 802.3 Local Area Network Guide, pp. 7-12 by National Semiconductor Corporation.
Bedlek Gregory J.
Berken James J.
Freeburg Thomas A.
Mitzlaff James E.
Ogasawara Roy T.
Hillman Val Jean F.
Kizou Hassan
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