Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation
Reexamination Certificate
2001-02-21
2004-03-30
Trinh, Sonny (Department: 2685)
Telecommunications
Receiver or analog modulated signal frequency converter
Local control of receiver operation
C455S259000, C455S262000, C455S264000, C327S156000, C327S157000, C375S374000, C375S375000
Reexamination Certificate
active
06714772
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technology effective for application to a PLL (Phase-Locked Loop) circuit provided with a plurality of VCO (Voltage-Controlled Oscillators) and capable of performing switching between oscillation frequencies, and a technology effective for application to a PLL circuit used as a local oscillator for generating an oscillation signal having a predetermined frequency, which is merged with a receive signal and a transmit signal in a wireless communication apparatus such as a portable or cellular telephone or the like capable of transmitting and receiving signals lying in plural bands, and to a wireless communication system using the PLL circuit.
As a mobile system like a portable or cellular telephone, may be mentioned, dual-band type cellular telephones capable of handling signals lying in two frequency bands, like, for example, a GSM (Group Special Mobile) using a band which ranges from 880 MHz to 915 MHz and a DCS (Digital Cellular System) using a band which ranges from 1710 MHz to 1785 MHz. In the cellular telephone, a PLL circuit is used as a local oscillator for generating an oscillation signal having a predetermined frequency, which is merged with a receive signal and a transmit signal. However, the cellular telephone capable of handling the signals lying within the two frequency bands much different from each other as described above encounters difficulties in covering the two frequency bands by one VCO from the viewpoint of circuit's characteristics. Thus, VCO corresponding to their frequencies are provided and selected according to a used frequency band.
FIG. 5
shows an example of a configuration of a conventional PLL circuit employed in a dual-band type cellular telephone. The PLL circuit comprises a divider
11
A which frequency-divides a reference frequency signal TCXO like 13 MHz into a signal R (hereinafter called a “reference side pulse”) of about 200 KHz substantially equal to a channel interval, a divider
11
B which frequency-divides a feedback signal F sent from either one of VCO into a pulse N (hereinafter called a “feedback side pulse”) having a frequency of 200 KHz identical to the reference side pulse R, a phase comparator
12
which compares the phase of the feedback side pulse N with that of the reference side pulse R and detects the difference in phase therebetween, a charge pump circuit
13
which delivers an electrical charge corresponding to the detected phase difference and draws or discharges it, a loop filter
14
which generates a voltage corresponding to the electrical charge supplied from the charge pump circuit
13
, two voltage-controlled oscillators (VCO)
15
A and
15
B each of which oscillates at a frequency corresponding to the generated voltage, and a selector switch
16
for selecting and feeding back oscillation outputs of these voltage-controlled oscillators
15
A and
15
B.
Incidentally, the interval between channels (frequency bands) is 200 KHz in the PLL circuit employed in the cellular telephone. In order to generate a local oscillation signal merged with a transmit/receive signal and identical to each selected channel in frequency from the PLL circuit for the purpose of selecting a desired channel from plural channels, a variable divider capable of changing a division ratio is used as the feedback side divider
11
B. When the switching between the channels is performed, the division ratio of the variable divider
11
B is changed to another according to a control signal sent from a system controller.
When a used band is changed from a GSM band to a DCS band or from the DCS band to the GSM band, the selection of the division ratio of the variable divider
11
B according to the control signal sent from the system controller and the switching between the outputs of the voltage-controlled oscillators (VCO)
15
A and
15
B by the switch
16
are substantially simultaneously carried out. Since, at this time, the time required to obtain the stabilization of a VCO output owing to the output changeover of the switch
16
is longer than a response time of a division output based on the selection of the division ratio of the variable divider
11
B, the switching to the VCO is normally carried out on ahead.
SUMMARY OF THE INVENTION
It has however been revealed that the PLL circuit employed in the conventional dual-band type cellular telephone has a problem in that a pull-in time of the PLL circuit becomes long upon band changeover due to the reasons to be described below.
FIG.
6
(A) shows the outputs of the dividers
11
A and
11
B and the output of the charge pump circuit
13
when the PLL circuit has been locked. As shown in the same drawing, the output (reference side pulse R) of the divider
11
A and the output (feedback side pulse N) of the variable divider
11
B are coincident in phase with each other. The output CP of the charge pump circuit
13
is kept constant at 0 V. When a division ratio n of the variable divider
11
B is lowered to decrease the oscillation frequency of the PLL circuit in this state, the cycle of the output (feedback side pulse N) of the variable divider
11
B becomes shorter than that of the output (reference side pulse R) of the divider
11
A as shown in FIG.
6
(B). Therefore, a negative current pulse CP is outputted from the charge pump circuit
13
so as to lower the frequency of each VCO. Since, at this time, the channel interval is 200 KHz within the same band and the division ratio is not greatly varied, the cycle of the feedback F becomes long and hence the PLL circuit is promptly brought to such a locked state as shown in FIG.
6
(A).
On the other hand, when the division ratio n of the variable divider
11
B is rendered high to increase the oscillation frequency of the PLL circuit, the cycle of the output (feedback side pulse N) of the variable divider
11
B becomes longer than that of the output (reference side pulse R) of the divider
11
A contrary to the above. Therefore, a positive current pulse CP is outputted from the charge pump circuit
13
so as to increase the frequency of each VCO. Further, the cycle of the feedback signal F becomes short and hence the PLL circuit is promptly brought to the locked state if the channel interval falls within the same band. Thus, the stabilization of the frequency is promptly carried out upon a change in the division ratio n of the variable divider
11
B with the selection of the channel within the same band.
Since, however, the changeover in the switch
16
is done upon the changeover of the band from the GSM band to the DCS band, the cycle of the output (feedback side pulse N) of the variable divider
11
B becomes abruptly short from a cycle T
1
in which a changeover in VCO is done as in the case of a timing t
1
shown in FIG.
7
. Therefore, a negative current pulse CP long in width is outputted from the charge pump circuit
13
so as to lower the frequency of the corresponding VCO. Further, even if two pulses outputted from the other divider (variable divider B) are introduced during one cycle of the output of one divider (reference side divider
11
A herein) as in the case of a cycle T
3
, the phase comparator
12
does not make a comparison with the two pulses. Therefore, the negative current pulse CP outputted from the charge pump circuit
13
becomes considerably long. As a result, the output of the VCO on the selection side is transferred or transitioned to the lowest frequency of a frequency variable range.
When the division ratio of the variable divider
11
B is changed to another with a timing t
2
in a cycle T
4
upon such a condition, the cycle of the output (feedback side pulse N) of the variable divider
11
B becomes long. However, the rising edge of the output (feedback side pulse N) of the variable divider
11
B becomes earlier than that of the output (reference side pulse R) of the reference side divider
11
A according to the division-ratio switching timing as in the case of a cycle T
5
. Thus, the negative current pulse CP would be outputted from the charge pump circuit
13
Kasahara Masumi
Yahagi Koichi
Mattingly Stanger & Malur, P.C.
Trinh Sonny
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