Pulse or digital communications – Systems using alternating or pulsating current
Reexamination Certificate
2001-03-01
2004-10-19
Tse, Young T. (Department: 2634)
Pulse or digital communications
Systems using alternating or pulsating current
C370S311000, C455S522000
Reexamination Certificate
active
06807235
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wireless communication apparatus processing intermittent data, and more particularly, to the structure of a data processing part for processing a base band signal in a wireless communication apparatus for receiving/transmitting intermittent data such as packet data. In addition, the present invention is suitable to communication terminal equipment used for processing packet data which is used for a mobile communication system of a CDMA (Code Division Multiple Access) method, etc.
2. Description of the Related Art
In these days, a wireless communication apparatus for processing a signal mainly on software has been devised corresponding to the variation and complication of wireless communication methods. As a software receiver, a wireless communication apparatus shown in
FIG. 11
is disclosed in, for example, a magazine of “Nikkei Electronics” published by Nikkei Business Publications, Inc., No. 732, pp.183-193. In this wireless communication apparatus, a received signal is converted into an intermediate frequency (IF) signal by a radio frequency (RF) circuit and, then, is inputted to a software receiver
39
. The inputted IF signal is converted into a digital signal by an A/D converter
33
, then, is quadrature-demodulated by a half-band filter (HBF)
34
, and is converted into an I-signal and a Q-signal. The I- and Q-signals are stored in a memory
35
.
Signal processing is subjected to the I- and Q-signals stored in the memory
35
on software by a digital signal processor (DSP)
36
. The DSP
36
transmits the processed signal to a central processing unit (hereinlater, abbreviated to a CPU)
37
as received data. The CPU
37
performs processes for upper layers such as call control operation, and outputs the processed output to the outside via external interface. A clock generator
38
supplies a clock signal necessary for the above-described components.
Then, in accordance with the wide spread of data communication in mobile communication, the ratio of packet data services to conventional audio circuit switched services is rapidly increased, thus arising a problem to increase the power consumption of a terminal. That is, communication data rate required for data communication is ten times or more as high as the communication data rate required for the audio communication. Also, in accordance therewith, the amount of processed signals increases and the power consumption of terminal equipment is marked.
However, the communication is not always performed in the packet data communication, and it is known that the period in which no packet data is received/transmitted is long.
For example, in an IMT-2000 mobile communication system, TSG RAN SWG1 TS25.211 (3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Physical channels and mapping of transport channels onto physical channels (FDD) (3G TS TS25.211 version 2.2.1) prescribes that a down signal to be transmitted to a terminal from a base station is communicated with a frame structure shown in
FIGS. 9A
to
9
C. As shown in
FIG. 9C
, the signal is structured by sequentially linking frames. As shown in
FIG. 9B
, one frame comprises fifteen slots. Further, as shown in
FIG. 9A
, one slot comprises a DPCCH data portion having control data (Pilot, TFCI, and TPC) and a DPDCH data portion in which user data (Data1 and Data2) is stored. Herein, the user data is transmitted only when the packet exists, and in cases except therefor, the transmission of the user data suspends. According to 3GPP TSG_RAN_WG1 TS25.214-v1.1.1, as shown in
FIG. 10
, if there is no downlink transmitting data to a terminal from a base station, the transmission of the DPDCH data portion suspends and only the DPCCH data portion is transmitted.
Moreover, unless the downlink transmitting data is generated for a predetermined period, the transmission of the DPCCH data portion suspends. On the other hand, if the downlink transmitting data is generated during the suspension of transmission of down data, the base station starts the transmission of the DPCCH data portion and the transmission of dummy DPDCH data portion, and the transmission of downlink DPDCH data portion in which the user data is stored resumes.
As mentioned above, the transmission and suspension of the user data are repeated in the packet data communication and, therefore, it is considered that the amount of processed signals to be averagely obtained is relatively small. However, the DSP in the conventional wireless communication apparatus needs to always supply a clock signal corresponding to a communication signal process at the maximum communication data rate and the power consumption cannot be effectively reduced if the amount of processed signals decreases.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a wireless communication apparatus for performing intermittent communication such as packet data communication, capable of effectively reducing the power consumption corresponding to the decrease in amount of processed signals for a period in which there is no user data.
In order to accomplish the above object, according to the present invention, there is provided a wireless communication apparatus having a wireless processing part for processing a wireless signal including intermittent data such as packet data and a data processing part for receiving/transmitting the intermittent data to/from the wireless processing part, wherein the data processing part includes a plurality of signal processing blocks whose signal processing periods are different such as a symbol, slot, and frame of signal processing units, a buffer memory which is provided between the plurality of signal processing blocks, a clock control part which supplies a clock signal to each of the plurality of signal processing blocks and the buffer memory, and a power source control part which supplies a power source to each of the plurality of signal processing blocks and the buffer memory. At least one of the plurality of signal processing blocks has means for watching which watches whether or not there is data to be processed in the subsequent signal processing block having a different processing period. The clock control part has means for controlling an operation to supply or suspend the clock signal to the subsequent signal processing block based on the watched result of the means for watching.
Also, in order to accomplish the above object, according to the present invention, the wireless communication apparatus further has means for controlling a power voltage to be supplied to the signal processing block and a memory block based on the watched result of the means for watching.
According to the present invention, by independently supplying the clock signals to a plurality of signal processing engines having different processing periods and independently controlling the power voltages, power consumption can be effectively reduced in an intermittent transmitting sequence of packet data because powers of an operating signal processing circuit and a memory can be decreased.
The features and advantages of the above description and those other than the above description according to the present invention will be further described in detail in the following embodiment.
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patent: 0655872 (1995-05-01), None
Gunn, James E. et al, “A Low-Power DSP Core-Based Software Radio Architecture,” IEEE Journal on Selected Areas in Communications, IEEE Inc., New York, NY, vol. 17, No. 4, Apr. 1999, pp. 574-590, XP-000824304.
Abidi, A. et al, “The Future of CMOS Wireless Transceivers,” Solid State Circuits Conference, 1997, Digest of Technical Papers, 43rd Isscc., 1997 IEEE International San Francisco, CA, Feb. 6-8, 1997, New York, NY, IEEE, Feb. 6, 1997, pp. 118-119, 440,
Suzuki May
Yano Takashi
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Tse Young T.
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