Telecommunications – Receiver or analog modulated signal frequency converter – Noise or interference elimination
Reexamination Certificate
2000-07-10
2004-05-11
Appiah, Charles (Department: 2686)
Telecommunications
Receiver or analog modulated signal frequency converter
Noise or interference elimination
C329S358000, C331S00100A, C455S141000, C455S164100
Reexamination Certificate
active
06735428
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wireless communication apparatus generating a decoding clock signal using a frequency synthesizer and more particularly relates to the wireless communication apparatus capable of preventing desensitization caused by harmonic of an operation clock signal.
2. Description of the Related Art
Concerning a receiving part in a wireless communication apparatus, when a strong disturbance wave exists near a receiving frequency, desensitization occurs because of amplification degeneration from saturation of a high frequency part or a like, and therefore a receiving sensitivity deteriorates.
Particularly, concerning a wireless selective calling receiver (such as a pager), for example, the wireless communication apparatus having multiple receiving line signal frequencies, since clock signal harmonic generated in a clock signal generating circuit in the wireless selective calling receiver becomes an disturbance wave and desensitization occurs, there are cases in that receiving sensitivity deteriorates as to a part of line signal frequencies.
FIG. 6
is a block diagram showing a conventional wireless communication apparatus, and
FIG. 7
is a view showing a relationship between a line signal frequency and a clock signal harmonic frequency in the conventional wireless communication apparatus.
The conventional wireless communication apparatus, as shown in
FIG. 6
, is provided with a clock signal generating circuit
301
, a control section
302
, a receiver/demodulator
303
, and a nonvolatile memory
304
.
The clock signal generating circuit
301
supplies an operating clock for the control section
302
.
The control section
302
controls a receiving operation of the receiver/demodulator
303
and executes processes such as decoding for a digital coded signal as a demodulation result from the receiver/demodulator
303
.
The receiver/demodulator
303
demodulates received wireless signal and outputs a demodulated signal consisting of a digital coded signal.
The nonvolatile memory
304
memorizes data such as an ID address in the demodulated signal, a receiving line signal frequency in the receiver/demodulator
303
and a like.
Additionally, for example, a frequency synthesizer is used as the clock signal generating circuit
301
. In the conventional wireless communication apparatus having multiple receiving line signal frequencies, like a wireless selective calling receiver, in order to convert a frequency of a received signal or a like, it is conventionally used that plural signals having required various frequencies are produced from stable standard frequency signals using a frequency synthesizer when plural station-frequency-signals and a like are generated (refer to Japanese Patent Application Laid-Open No. Hei5-152903, Japanese Patent Application Laid-Open No. Hei9-008688).
Further, recently, a frequency synthesizer is also used as a clock signal generating circuit for generating a clock signal decoding an encoded-received-demodulated signal.
Next, explanations will be given of operation of the conventional wireless communication apparatus with reference to FIG.
6
.
A high frequency signal inputted through an antenna (not shown) and consisting of a wave modulated by a predetermined modulation mode is inputted into the receiver/demodulator
303
.
The control section
302
controls the receiver/demodulator
303
so that only the high frequency signal of a required line signal frequency in response to data of received line signal frequency memorized in the nonvolatile memory
304
.
The receiver/demodulator
303
demodulates the received high frequency signal and then outputs the demodulated signal as a digital signal of a predetermined encoding form.
The control section
302
decodes this encoded signal using an operation clock signal from the clock signal generating circuit
301
. In addition, the control section
302
outputs decoded result data onto a display or a like when an ID address in decoded results data coincides with the ID address memorized in the nonvolatile memory
304
.
Concerning the wireless communication apparatus shown in
FIG. 6
, as shown in
FIG. 7
, a constant range P of front and back of a line signal frequency f
0
, for example, a range of f
0
±&Dgr;f
0
is the range in which desensitization occurs. When a disturbance wave exists in this range, receiving sensitivity deteriorates.
When a harmonic frequency m·f
LKC
of a clock signal is within this range, it effects to a received input and becomes the disturbance wave, receiving sensitivity deteriorates compared with a frequency range outside this range.
In the conventional wireless communication apparatus shown in
FIG. 6
, the frequency f
CLK
of a clock signal generated in the clock signal generating circuit
301
is approximately constant. Therefore, there is a problem in that receiving sensitivity deterioration can not avoided since a harmonic m·f
CLK
of the clock signal enters the frequency range of f
0
±&Dgr;f
0
in which desensitization occurs with a used line signal frequency when a number of receiving lines is large.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a wireless communication apparatus having plural receiving line signal frequencies and preventing desensitization caused by harmonic of an operation clock signal.
According to a first aspect of the present invention, there is provided a wireless communication apparatus including a receiver/demodulator for receiving a line signal of a designated frequency and for demodulating the line signal, a control section for decoding a demodulated line signal with a clock signal, and a clock signal generating circuit for supplying the clock signal for the control section, and wherein the control section controls the clock signal generating circuit in response to the line signal frequency to change a frequency of the clock signal so that harmonic of the clock signal does not exist in a desensitization range corresponding to the line signal frequency.
In the foregoing, a preferable mode is one wherein the clock signal generating circuit includes a standard oscillator generating a signal of a standard frequency, a divider for dividing the clock signal, a phase comparator for detecting a phase error between the divided clock signal and a standard frequency signal and a VCO (Voltage Controlled Oscillator) for changing an oscillating frequency in response to the phase error and wherein the frequency of the clock signal outputted from the VCO is changed by changing the dividing number of the divider in accordance with control by the control section.
Also, a preferable mode is one wherein the control section sequentially changes the dividing number of the divider and controls the clock signal generating circuit to generate the clock signal while determining whether a clock signal harmonic frequency exists in the desensitization range corresponding to the line signal frequency in accordance with the line signal frequency or not, so that the clock signal harmonic frequency does not exist in the desensitization range corresponding to the line signal frequency.
Also, a preferable mode is one wherein the control section determines whether the clock signal harmonic frequency is close to an upside or a downside in the desensitization range, and then controls the clock signal harmonic frequency to exist just outside of the desensitization range.
Also, a preferable mode is one wherein the control section calculates a dividing number of dividing part necessary so that the clock signal harmonic frequency does not exist in the desensitization range corresponding to the line signal frequency in response to the line signal frequency.
Also, a preferable mode is one further including a memory for memorizing the calculated dividing number so as to correspond with the line signal frequency, and wherein the control section controls the clock signal generating circuit to generate the clock signal using the memorized dividing number
Appiah Charles
Ly Nghi H.
NEC Corporation
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