Wired "OR" bus evaluator for logic simulation

Details Wired "OR" bus evaluator for logic simulation Wired "OR" bus evaluator for logic simulation

1988-03-07

1989-04-11

Zache, Raulfe B.

Boots, shoes, and leggings

364900, 364578, 371 23, G06F 1520, G06F 1574, G06F 7544, G06F 944

Patent

active

048211737

ABSTRACT:
The present invention consists of a hardware simulator with bus evaluator logic for use in simulating and fault grading of very large scale digital circuits containing buses. In this invention the status of a bus is continously upgraded each time a primitive is evaluated that has an output coupled to the bus. As bus driver primitives are evaluated, the state of the bus is determined on the fly and stored in an accumulator register, called the bus register. Evaluation of the bus continues using the data stored in the bus register and the state of each driver until all drivers have been evaluated. After the last bus driver is evaluated the state of the bus is known and the bus primitive is assigned the value, or state, stored in the bus register hardware and is passed to all receivers on the bus.

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