Wired-AND FET logic gate

Details Wired-AND FET logic gate Wired-AND FET logic gate

1984-10-19

1987-07-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307450, H03K 19094

Patent

active

046804846

ABSTRACT:
A logic gate for use as a fundamental building block in more complex digital circuitry. The logic gate has multiple wired-AND input circuits, each capable of accepting multiple inputs, and each connected to a single pull-up field-effect transistor (FET), and to a common power supply. The wired-AND input circuits are ORed together and their signals level-shifted by diodes, before application to a FET output circuit that has one gate terminal and multiple drain output terminals. To facilitate expansion of the logic, these output terminals are connectable, either singly or together with outputs from other similar gates, as inputs to similar gates. The logic gate of the invention has a very low parts count compared with other logic topologies for the same purpose, and has an extremely favorable propagation delay-power product.

REFERENCES:
patent: 4404480 (1983-09-01), Ransom et al.
patent: 4405870 (1983-09-01), Eden
patent: 4418291 (1983-11-01), Watson, Jr.
patent: 4485316 (1984-11-01), Nuzillat et al.
Nuzillat et al., "Low Pinch-Off Voltage F.E.T. Logic (L.P.F.L.): LSI Oriented Logic Approach Using Quasi-Normally Off GaAs MESFETs"; IEEE Proc., vol. 127, Pt. 1, No. 5, pp. 287-296; 10/1980.

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