Wirebond over post passivation thick metal

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S759000, C257S781000, C257SE23020

Reexamination Certificate

active

08030775

ABSTRACT:
A chip assembly includes a semiconductor chip and a wirebonded wire. The semiconductor chip includes a passivation layer over a silicon substrate and over a thin metal structure, a first thick metal layer over the passivation layer and on a contact point of the thin metal structure exposed by an opening in the passivation layer, a polymer layer over the passivation layer and on the first thick metal layer, and a second thick metal layer on the polymer layer and on the first thick metal layer exposed by an opening in the polymer layer. The first thick metal layer includes a copper layer with a thickness between 3 and 25 micrometers. The wirebonded wire is bonded to the second thick metal layer.

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