Wire structures minimizing coupling effects between wires in...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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C716S129000, C716S130000

Reexamination Certificate

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07962880

ABSTRACT:
A method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement.

REFERENCES:
patent: 5297094 (1994-03-01), Rastegar
patent: 6189133 (2001-02-01), Durham et al.
patent: 6388277 (2002-05-01), Kobayashi et al.
patent: 6772406 (2004-08-01), Trimberger
patent: 6999375 (2006-02-01), Jung et al.
patent: 2005/0216876 (2005-09-01), Proebsting et al.
patent: 2006/0143586 (2006-06-01), Suaya et al.
patent: 2006/0236290 (2006-10-01), Makino
patent: 2007/0226673 (2007-09-01), Habitz et al.

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