Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2001-09-05
2004-09-07
Nelms, David (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S786000, C174S258000, C438S617000
Reexamination Certificate
active
06787926
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to wire bond interconnects for integrated circuit chips, and more particularly to a wire bond interconnect using a stitch bond on an integrated circuit chip pad.
BACKGROUND OF THE INVENTION
A variety of interconnects systems for making electrical connection between a substrate and an integrated circuit chip, and between integrated circuit chips in a multiple chip stacked assembly. Warren, U.S. Pat. No. 5,905,639, issued May 18, 1999, discloses a three-dimensional circuit structure that interconnects an integrated circuit chip, along with additional active devices and passive components, to a substrate by way of a high-density multichip interconnect decal disposed on the integrated circuit chip. The three-dimensional circuit structure includes the substrate, integrated circuit chip attach to the top of the substrate, and high-density multichip interconnect decal attached to the integrated circuit chip. One or more passive components and relatively small active devices are attached to the top of the high-density multichip interconnect decal. A plurality of the three-bond, daisy-chained wedge bonds are used to interconnect active devices and passive components to the substrate by way of the high-density multichip interconnect decal. Each wedge bond includes a wire that is initiated at the high-density multichip interconnect decal bond pad, an intermediate stitch bond at the integrated circuit chip bond pad, and terminates at the substrate bond pad.
Lake et al., U.S. Pat. No. 6,114,239, issued on Sep. 5, 2001, discloses an integrated circuit chip die pad. A supporting substrate includes circuit traces fabricated from an electrically conductive material such as copper. Exposed aluminum on the die pad is electroless copper plated to form a copper layer. Electroless copper plating is well known to those skilled in the art. This reference indicates that although copper is the metal of choice in the preferred embodiments, other conductive metals may be used in place of the copper. A conductive epoxy is formulated to have a copper oxide reducing agent and is applied to the copper layer overlying the contact. The copper layer forms in interface layer on the aluminum contact area in order to provide a desired surface for the conductive epoxy. The conductive layer and the contact area form the metal bond pad portion and the conductive epoxy forms the conductive epoxy portion of the electrical bonding interconnect. This reference also indicates that a metal other than copper may be plated onto the contact area, and in such case the oxide reducing agent in the conductive epoxy is selected to reduce the oxides formed before and/or during the process. The integrated circuit chip die pad is positioned over a supporting substrate such that the contact areas on both are aligned. The cured epoxy functions as a standoff between the die pad and the substrate. The epoxy is then cured, binding the die pad and the substrate together. A wire bond may be used to electrically connect the supporting substrate to an external electrical connection.
Liao et al., U.S. Pat. No. 6,075,281, issued on Jun. 13, 2000, discloses lead fingers that have inclined tip portions for achieving an improved wire bond. The inclined tip portions of the lead fingers can be formed in a stamping process with an angle on the top surface of the inclined tip portions measured at smaller than 30° from a horizontal plane of the lead finger. The inclined angle should be between about 5° and about 30°, and more preferably the angle should be between about 5° and about 20°. A wedge bond is formed on the inclined tip portion of the lead finger having improved thickness and thermal stress endurance. The thermal stress endurance may be improved by at least 20% and preferably at least 50% when tested in a thermal cycling test between 150° C. and −65° C. A wire bonding ball is formed on the bonding pad of the integrated circuit chip.
Ball, U.S. Pat. No. Re 36,613, discloses a stacked integrated circuit chip die device mounted on a paddle with the integrated circuit chip dies adhesively connected to each other by a controlled thickness thermoplastic adhesive layer. A group of four dies are attached to the paddle by a controlled adhesive layer. Each of the die bonding pads in double rows are electrically connected to multiple lead fingers by thin gold or aluminum wire, with gold being the preferred metal. The critical bonding method used at the die end pads is an ultrasonic ball bond as named by the shape of the bond. The other end of the gold wire is attached to a lead finger by a wedge bond, which is also an ultrasonic bond wherein ultrasonic energy is used to heat the wire as it is compressed against the lead finger. This reference indicates that a wedge bond is not used on the integrated circuit chip die because the bonding machine contacts the bonding surface and could damage this critical surface.
Other methods of making wire interconnects between a substrate and an integrated circuit chip, and in particularly between integrated circuit chips in on a multichip stacked device are known to those skilled in the art.
FIG. 1
illustrates a prior art multichip stacked device
8
including a first integrated circuit chip
10
stacked on top of a second integrated circuit chip
12
and with an adhesive layer
14
securing the chips
10
,
12
together. The stacked chips
10
,
12
are attached to an underlying first substrate
16
which in this case is a ball grid array. First and second bond pads
20
,
22
are provided on the first substrate
16
. A first wire
24
is connected from the first substrate
16
, wherein the first wire
24
has a wire ball bond
26
connected to the first bond pad
20
and a stitch bond
28
connected to a wire bond stud bump
30
formed on a bond pad
32
of the first integrated circuit chip
10
. A second wire
34
includes a ball bond
28
connected to a bond pad
40
on the second integrated circuit chip
12
and a stitch bond
36
formed on the second bond pad
22
of the first substrate
16
. Forming a stitch bond on the integrated circuit chips
10
,
12
is avoided in order to eliminate the risk of causing damage to the chips by forming a stitch bond on a bond pad of a chip because stitch bonding uses ultrasonic vibration and pressure.
FIG. 2
illustrates a second multichip stacked device
42
which also includes a first integrated circuit chip
44
stacked on top of a second integrated circuit chip
46
with a first adhesive layer
48
securing the two chips together. The stacked integrated circuit chips
44
,
46
are secured to a substrate
50
which in this case is a standard printed wire board. Similar to
FIG. 1
, wires
52
,
54
are provided between the substrate
50
and the second integrated circuit chip
44
. The first wire
52
includes a stitch bond
56
formed on a wire stud bump
57
formed on contact pad
59
of the second integrated circuit chip
44
and a ball bond
58
formed on a bond pad provided on the substrate
50
. The second wire
54
provides a stitch bond
60
formed on a bond pad provided on the first substrate
50
and a ball bond
62
on a first integrated circuit chip
44
. Wires
62
,
64
are provided between the first integrated circuit chip
44
and the second integrated circuit chip
46
. The first wire
62
includes a ball bond
72
formed on a bond pad
74
of the second integrated circuit chip
46
. The other end of the wire
62
has a stitch bond
75
connected to the wire stud bump
77
formed on a bond pad
78
of the first integrated circuit chip
44
. The second wire interconnects
64
includes a stitch bond
66
formed on a wire stud bump
68
on a contact pads
70
of the second integrated circuit chip
66
, and the other end of the second wire interconnect
64
includes a ball bond
68
formed on a contact pad
70
on the first integrated circuit chip
44
.
FIGS. 3A-H
illustrate the steps of a prior art method of making a wire interconnect between two integrated circuit chips. A first semiconductor device
8
Chen Chih-Chiang
Tsao Pei-Haw
Wang Chung-Yu
Cruz Lourdes (Elle)
Nelms David
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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