Metal fusion bonding – Process – Plural joints
Reexamination Certificate
2001-07-06
2003-05-13
Elve, M. Alexandra (Department: 1725)
Metal fusion bonding
Process
Plural joints
C228S001100, C257S673000, C438S613000
Reexamination Certificate
active
06561411
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89127630, filed Dec. 22, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a wire bonding process and a wire-bonding structure. More particularly, the invention relates to a wire-bonding process performed according to reverse bonding fashion.
2. Description of the Related Art
As the era of information technology progresses, the transmission and processing of information and documents are extensively carried out through electronic equipment. Accompanying the progress of technology, many electronic products with more convenient features are promoted with great success, as mobile phones, computers, audio-video articles, etc. Electronic products usually comprise semiconductor devices packaged into electronic packages. An important step in semiconductor device packaging process is the wire bonding that establishes the electrical connection within the electronic package between the semiconductor device and the carrier of the semiconductor device.
Referring to FIG.
1
and
FIG. 2
, cross-sectional views schematically illustrate the conventional reverse bonding process disclosed in U.S. Pat. No. 5,328,079 issued to Mathew et al. In
FIG. 1
, the conventional wire-bonding process comprises first, providing a chip
100
. The chip
100
has an active surface
102
and a corresponding back surface
104
, wherein the active surface
102
further includes at least a first contact pad
106
. A substrate
150
is further provided with a surface
152
on which at least a second contact pad
154
is formed, wherein the back surface
104
of the chip
100
is bonded to, for example, the surface
152
of the substrate
150
. By means of a wire-bonding machine (not shown), a conductive bump
108
is formed on the first contact pad
106
of the chip
100
.
Referring to
FIG. 2
, a reverse bonding then is performed using the wire-bonding machine. First, a prominence
182
is formed on the second contact pad
154
in ball-bonding fashion. A head of the wire bonding machine (not shown) then moves from the formed prominence
182
to the conductive bump
108
on the first contact pad
106
of the chip
100
, wherein the head of the wire-bonding machine continuously releases a conductive material forming a wire
180
while moving. The wire
180
hence formed is bonded to the conductive bump
108
in a stitch-bonding fashion.
In the foregoing wire bonding process, because the conventionally fixed height of the bump
108
is not sufficient, a shorting contact of the wire
180
with the edge of the chip
100
may occur at the location
190
proximate to the edge of the chip
100
. As a result, the reliability of the electronic packaging structure is reduced. Moreover, the wire
180
may easily peel off from the bump
108
when the packaging structure is submitted to a contingent external force.
SUMMARY OF THE INVENTION
An aspect of the invention therefore is to provide a wire-bonding process and a wire-bonding structure that can improve the quality of the electrical connection through bonding-wires, which thus improves the reliability of packaging structures.
Another aspect of the present invention is to provide a wire-bonding process and a wire-bonding structure that ensures the wire bonding.
To attain at least the foregoing objectives, the present invention proposes a wire-bonding process that comprises the following steps. A chip is provided with at least a first contact pad thereon. A chip carrier is further provided with at least a second contact pad thereon. A plurality of stacked conductive bumps are formed over the first contact pad of the chip. A conductive wire is formed such that it connects the second contact pad of the chip carrier to the stacked conductive bumps over the first contact pad of the chip. The formed conductive wire connects the second contact pad via a prominence and the first contact pad on the uppermost conductive bump of the stacked bumps.
To attain at least the foregoing objectives, the present invention proposes a wire bonding process that, according to another embodiment, comprises the following steps. A chip is provided with at least a first contact pad thereon. A chip carrier is further provided with at least a second contact pad thereon. A first conductive bump is formed on the first contact pad of the chip. A conductive wire is formed such that the conductive wire connects the second contact pad of the chip carrier and connects onto the first conductive bump over the first contact pad of the chip. The formed conductive wire connects the second contact pad via a prominence. A second conductive bump is formed on the conductive wire and over the first conductive bump.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5328079 (1994-07-01), Mathew et al.
patent: 5740956 (1998-04-01), Seo et al.
patent: 5908317 (1999-06-01), Heo
patent: 6181569 (2001-01-01), Chakravorty
patent: 6239366 (2001-05-01), Hsuan et al.
patent: 6396155 (2002-05-01), Nukiwa et al.
patent: 6420256 (2002-07-01), Ball
patent: 2002/0014685 (2002-02-01), Tsukahara
patent: 2002/0105069 (2002-08-01), Kawahara et al.
Advanced Semiconductor Engineering Inc.
Elve M. Alexandra
J.C. Patents
Pittman Zidia
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