Wiper controller with fault detector device

Details Wiper controller with fault detector device Wiper controller with fault detector device

2001-11-14

2003-09-23

Nappi, Robert E. (Department: 2837)

Electricity: motive power systems

Periodic, repetitious or successive operations control of...

C318S442000, C318S444000, C318S445000, C318S280000, C318S281000, C318S282000, C318S283000, C318SDIG002, C015S250001, C015S256500, C015S256510

Reexamination Certificate

active

06624604

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a wiper control device, in which a semiconductor switch element such as a MOS-FET (metal oxide semiconductor field-effect transistor) is employed as a drive-control element of a motor.
(2) Description of the Related Art
A conventional wiper control device is disclosed in Japanese Patent Application Laid-Open No. H9-193748. As shown in
FIG. 21
, in this wiper control device, when a combination switch
17
is set in an intermittence mode (INT), a driving circuit
20
turns a switch element
19
ON to start a motor
15
, thereby allowing a wiper to make one reciprocating motion. When the wiper makes one reciprocating motion, a terminal P of a wiper switch
16
is connected to a terminal Q and the driving circuit
20
turns the switch element
19
OFF to cut off the electric power supply supplied to the motor
15
. When the terminal P of the wiper switch
16
is connected to the terminal Q, a terminal K at the battery voltage side is connected to a terminal J at the ground side by way of a contact terminal Ti and a brake resistance
18
to control the motor
15
, thereby the wiper quickly stops.
There is another driving circuit of a wiper motor as shown in FIG.
6
.
Qb is a P-channel-type MOS-FET, which acts as a semiconductor switch element for supplying or cutting a driving voltage supplied to a wiper motor M
2
through its ON/OFF motion. A drain thereof is connected to the wiper motor M
2
, a source is connected to a power supply (battery) VG, and a gate is connected to a control output terminal of a controller (not shown in the figure).
Qa is an N-channel-type MOS-FET, which acts as a semiconductor switch element for carrying out a halting action of the wiper motor M
2
through its ON/OFF motion. A drain thereof is connected to a drain of a MOS-FETA (Qa) by way of a Zener diode ZD, a source is grounded, and a gate is connected to the control output terminal of the controller.
The conventional wiper control device described above has the following problem.
When a short circuit takes place with VG (battery voltage) or GND (ground) at the high side (FET drain) of the motor, an abnormal current (large current) flows into a MOS-FET (Qa) (hereinafter, FETA (Qa)) for halting the motor or a MOS-FET (Qb) (hereinafter, FETB (Qb)) for driving the motor.
At this time, the FET (field-effect transistor) possibly generates heat making the wiper control device to fire or to generate heat.
In order to prevent the above accident from occurring, an FET including a known overheat-cutting protective function, a constitution of which is shown in
FIG. 5
, is employed as a FET for driving the motor or for halting the motor.
As shown in
FIG. 5
, an overheat-cutting protective circuit works as a temperature detection circuit and compares a voltage at a contact between a current source connected to a gate of the FETA (Qa), to which a control signal is supplied from a control output of the controller by way of a resistance R, and a temperature detection part consisting of a plurality of diodes Z
1
and Z
2
, which detect the heat generation of the FETA (Qa), with a reference voltage of a reference voltage source, thereby outputting the result of the comparison as the temperature detection.
After the output of the temperature detection from the temperature detection circuit is supplied to a latch circuit, the output is input to a gate-cutting circuit, which is connected between the gate of the FETA (Qa) and the source, and a gate potential of the FETA (Qa) is set up low level, thereby rendering the FETA (Qa) from ON to OFF, that is, cutting the electric supply.
However, an action of the overheat-cutting protective function brings about a large stress to the FET and a repetition thereof brings about a rapid deterioration of the FET.
Since the overheat-cutting protective function is latched once it is acted, the protective action (i.e., latched state) is not removed unless the input of the action signal to the gate is removed.
However, in this wiper system, regarding either the FETA (Qa) or FETB (Qb), since the ON/OFF motion thereof is repeated for every intermittent action of the wiper, therefore the action of the overheat-cutting protective function is carried out for every ON/OFF motion of the FET. As a result, when the wiper control device is used for a long period of time in an abnormal condition, the action of the overheat-cutting protective function is repeatedly carried out, causing a significant deterioration of the reliability of the circuit.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to solve the above problem and to provide a wiper control device, in which the abnormal condition of the FET is detected by distinguishing the action of the overheat-cutting protective function normally difficult to be detected with measuring the drain voltage of the FET, and by which the control of the pertinent FET is restrained upon the detection of abnormality, thereby preventing the accident in the wiper control device from occurring.
In order to attain the above objective, as shown in a basic constitutional illustration of
FIG. 1
, the present invention is to provide a wiper control device comprising a controller for outputting a control signal, which responds to a drive or halt of a wiper motor, to a first field-effect transistor and a second field-effect transistor,
wherein the wiper motor is connected between a drain of the first field-effect transistor and ground or between the drain and a power supply, the first and second field-effect transistors are connected in series between the power supply and ground through the drain, and the controller comprises:
drain voltage detection means for detecting a drain voltage of the first field-effect transistor or the second field-effect transistor;
short circuit detection means for detecting a short circuit of a drain circuit on the basis of an abnormal value of the detected drain voltage;
count means for counting the number of times of the detection of the short circuit;
comparison means for comparing the number of times of the detection of the short circuit with a predetermined reference number of times; and
judgment means for judging an occurrence of the short circuit when the number of times of the detection of the accident consecutively reaches the reference number of times. Thereby, the field-effect transistor (FET) judged involved with an occurrence of the short circuit is set OFF and the control of the pertinent FET is halted thereafter. Preferably, the short circuit detection means comprises:
first detection means for detecting a short circuit of the drain coming into contact with ground when the drain voltage approximates to the ground potential upon the first field-effect transistor being on; and
second detection means for detecting a short circuit of the drain coming into contact with the power supply when the drain voltage approximates to a power supply voltage upon the second field-effect transistor being on.
Thereby, when the potential generated at the drain is not a normal potential upon the action of the first field-effect transistor or the second field-effect transistor being on, a matter of the short circuit is judged on the basis of the potential generated at the drain.
Preferably, the short circuit detection means is provided with delay means for taking in the detected drain voltage with a specific delay time. Thereby, the drain voltage is output with a specific delay time, preventing an instantaneously changed drain voltage from being taken in as a voltage judged indicating an accident.
Preferably, the delay means is constituted by a digital filter, thereby the delay time can be minutely set up and facilitated to be changed.


REFERENCES:
patent: 5041940 (1991-08-01), Sullivan
patent: 6023107 (2000-02-01), Grass
patent: 6400110 (2002-06-01), Yabe et al.
patent: 39 36 544 (1990-06-01), None
patent: 2 368 408 (2002-05-01), None
patent: 4-278867 (1992-10-01), None
patent: 9-193748 (1997-07-01), None

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