Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2000-02-04
2003-07-01
Thomson, W. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S015000, C703S014000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06587815
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to detection of, and compensation for, noise in large digital circuits.
BACKGROUND OF THE INVENTION
The scaling of transistor size in digital integrated circuits has also led to the shrinking of wire or circuit trace dimensions. A proportionate scaling of wire heights will produce a proportionate increase in wire resistance to electrical current. To avoid this problem, the reduction scale factor for wire height has often been larger (closer to 1) than the scale factor for a horizontal dimension. This has produced wire aspect ratio changes, as illustrated in
FIG. 1A
(before scale change) and
FIG. 1B
(after scale change). Further, the spacing distance d between adjacent wires is also reduced by a scaling factor. All these results contribute to an increase in capacitive coupling to adjacent wires and to a decrease in capacitive coupling to so-called quiet planes located above and below the wires. Further, shrinking of the vertical dimension of a wire, although not as pronounced as shrinking in other directions, increases wire resistance and makes the problem of circuit noise worse.
Increases in coupling coefficients and wire resistances contribute to production of much larger noise voltages in deep sub-micron designs than was present in previous generations of semiconductor devices. These voltages typically push a digital gate into the amplifying region of its transfer characteristic, turning a traditionally noise rejecting gate into a noise amplifying stage. Induced noise voltages can create several different problems on chip. Of these, one is most concerned with detection of faulty logic transitions that are triggered by noise, especially irrevocable logic transitions, such as the firing of a precharged gate or the corruption of the data in a storage element.
Noise problems typically depend upon the data set, the testing frequency and process variations. Larger test vector sets are needed to increase the probability that the chip encounters a condition where the effect of coupling noise can be observed. Values for noise voltages and spikes cannot be easily measured on silicon, because the introduction of a probe to a given net dramatically alters its coupling coefficient and also alters the magnitude of the noise induced in the net. As such, noise related problems are not easily reproducible and are extremely difficult to debug, or even to identify as a noise effect, because all other probable causes must first be ruled out. A significantly higher cost in time and money is paid for debugging noise induced problems.
A good noise detection methodology must ensure that a large and complex chip such as a modern microprocessor, can be produced and tested without adding significant delay or cost to the noise detection or noise debugging steps.
What is needed is a method for efficiently and quickly analyzing the results of noise in a large digital circuit and for determining and applying limits on voltage noise amplitude, below which a noise pulse will not propagate from one module to another module on a network.
SUMMARY OF THE INVENTION
These needs are met by the invention, which provides two criteria for confining the effects of generation of a noise pulse, based on tests that characterize the response of different classes of transistors to noise pulses of varying pulse magnitudes. The invention also provides a software noise analysis tool, “noisetool”, that detects large coupling noise voltages induced in a microprocessor chip. The following noise detection criterion is adopted: a noise pulse should not propagate through an amplifying stage, and all noise induced at any site on a net should be induced only by aggressor signals at nearest neighbor sites, not by any preceding logic stages.
The noisetool uses a layout parasitic extracted netlist as a starting point and performs flat file and/or hierarchical analyses. All interconnect parasitic elements, usually capacitive and resistive elements, are read from this netlist. In a flat file analysis, the gate and diffusion capacitances of the transistors are calculated based on the transistor models adopted and on transistor sizing information contained in the netlist. Because a bias-independent linear resistance is assumed for the transistor associated with the “victim” line, this resistance is computed based on the device parameters. When a hierarchical analysis is performed, the capacitive loading and/or drive resistance of the sub-circuit ports are preferably obtained from characterized data files.
Where each of two or more aggressor gates can produce a transition signal whose transition time is within a selected switching time interval, determined with reference to a subsequent time a victim gate switches, the combined effects of all such aggressor signals are included in determining if a circuit permits noise pulse propagation. The invention covers situations where two or more aggressor gates may fire at separate and independent times within the switching time interval and the situation where the aggressor gates fire substantially simultaneously.
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“Statistical Method of Noise Estimation in a Synchronous System”, D. Rude, IEEE Transaction on Components, Packaging, an Manufacturing Technology—Part B, vol. 17, No. 4, Nov. 1994.*
“S-Parameter Based Technique for Simultaneous Switching Noise Analysis in Electronic Packages” Z. Jin, IEEE Transactions on Advanced Packaging, vol. 22, No. 3, Aug. 1999.*
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Aingaran Kathirgamar
Haritsa Manjunath D.
Varadadesikan Lakshminarasimhan
Ferris Fred
Martine & Penilla LLP
Sun Microsystems Inc.
Thomson W.
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