Window-type multi-chip semiconductor package

Details Window-type multi-chip semiconductor package Window-type multi-chip semiconductor package

2002-12-04

2004-03-09

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S723000, C257S784000, C257S787000

Reexamination Certificate

active

06703713

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a window-type multi-chip semiconductor package in which a substrate formed with an opening is used as a chip carrier for accommodating a plurality of chips thereon.
BACKGROUND OF THE INVENTION
A window-type semiconductor package employs advanced packaging technology, characterized in the use of a substrate formed with at least an opening penetrating through the same, allowing a chip to be mounted over the opening on the substrate and electrically connected to the substrate by means of a plurality of bonding wires formed through the opening. This structure is beneficial of shortening length of the bonding wires to thereby enhance electrical transmission and performances of the chip.
U.S. Pat. No. 6,218,731 discloses a window-type semiconductor package
1
, as shown in
FIG. 4
, comprising: a substrate
10
formed with an opening
100
penetrating through the substrate
10
; a chip
11
mounted on an upper surface
101
of the substrate
10
, with bond pads
111
formed on an active surface
110
of the chip
11
being exposed to the opening
100
; a plurality of bonding wires
12
formed through the opening
100
and bonded to the bond pads
111
of the chip
11
, for electrically connecting the active surface
110
of the chip
11
to a lower surface
102
of the substrate
101
; a first encapsulant
13
formed on the upper surface
101
of the substrate
10
for encapsulating the chip
11
; a second encapsulant
14
formed on the lower surface
102
of the substrate
10
, and filling into the opening
100
for encapsulating the bonding wires
12
; and a plurality of solder balls
15
implanted on the lower surface
102
of the substrate
10
at area free of the second encapsulant
14
, the solder balls
15
acting as I/O (input/output) ports for electrically connecting the semiconductor package
1
to an external device such as a printed circuit board (PCB, not shown).
In order to improve operational speed and electrical performances, Taiwan Patent Publication No. 407354 discloses a window-type dual-chip semiconductor package
1
′, as shown in
FIG. 5
, wherein a chip
11
(hereinafter referred to as “first chip”) of the above semiconductor package
1
is stacked with a second chip
16
thereon in a back-to-back manner that a non-active surface
160
of the second chip
16
is attached to a non-active surface
112
of the first chip
11
. An active surface
161
of the second chip
16
is opposed to an active surface
110
of the first chip
11
, and thus, bond pads
162
formed on the active surface
161
of the second chip
16
are substantially opposed in position to bond pads
111
on the first chip
11
; as a result, bonding wires
12
′ for electrically connecting the bond pads
162
of the second chip
16
to an upper surface
101
of a substrate
10
are much longer than bonding wires
12
for electrically connecting the bond pads
111
of the first chip
11
to the substrate
10
. This arrangement thereby leads to significant drawbacks; longer bonding wires
12
′ would delay electrical transmission for the second chip
16
, making the second chip
16
not comparable in operational speed to the first chip
11
. Moreover, due to the back-to-back stacking of the first and second chips
11
,
16
with conductive elements such as bond pads
111
,
162
thereof being opposed in position, customarily referred to as pin-to-pin incompatibility, it is therefore not applicable to stack identical chips.
U.S. Pat. No. 6,281,578 discloses a window-type multi-chip (three-chip) semiconductor package
1
″, as shown in
FIG. 6
, wherein a first chip
11
and a second chip
16
are mounted on an upper surface
101
of a substrate
10
, and the first and second chips
11
,
16
are spaced apart from each other by an opening
100
penetrating through the substrate
10
in a manner that the first and second chips
11
,
16
are respectively disposed at opposing sides with respect to the opening
100
. A third chip
17
is mounted oil a lower surface
102
of the substrate
10
and over the opening
100
, allowing bond pads
171
formed on an active surface
170
of the third chip
17
to be exposed to the opening
100
; the exposed bond pads
171
are bonded with bonding wires
12
″ to electrically connect the third chip
17
to the substrate
10
and the second chip
16
. The first chip
11
is also electrically connected to the second chip
16
and the substrate
10
by means of bonding wires
12
″. Moreover, the substrate
10
may be integrally formed with a plurality of leads
18
, which act as
110
ports for electrically connecting the chips
11
,
16
,
17
to an external device such as PCB (not shown). By the structural arrangement of the semiconductor package
1
″ with active surfaces
110
,
160
,
170
of the chips
11
,
16
,
17
being attached to the substrate
10
in a face-up manner, the above discussed drawbacks rendered by back-to-back chip stacking can thus be eliminated. However, as the chips
11
,
16
,
17
are separately mounted to different upper and lower surfaces
101
,
102
of the substrate
10
, bonding wires
12
″ e.g. for interconnecting the second and third chips
16
,
17
are hard to be effectively reduced in length, thereby adversely affecting improvement in electrical transmission.
Other related prior arts, including U.S. Pat. Nos. 6,265,763 and 6,414,396, also provide a window-type multi-chip package structure, but fail to disclose stacking of chips on the same surface of a substrate so as to effectively reduce wire length and enhance electrical performances of the package structure.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a window-type multi-chip semiconductor package, wherein a plurality of chips are stacked on the same surface of a substrate formed with an opening, and conductive elements such as bond pads formed on the chips are arranged toward the same direction, so as to shorten wire length and enhance electrical transmission as well as improve electrical and operational performances of the semiconductor package.
Another objective of the invention is to provide a window-type multi-chip semiconductor package, which can stack a plurality of chips having centrally-situated bond pads on the same surface of the substrate formed with an opening.
In accordance with the above and other objectives, the present invention proposes a window-type multi-chip semiconductor package, comprises: a substrate having an upper surface and a lower surface opposed to the upper surface, and formed with at least an opening penetrating through the substrate; at least a first chip and a second chip each having an active surface and a non-active surface opposed to the active surface, wherein the active surfaces of the first and second chips are mounted on the upper surface of the substrate respectively at opposing sides with respect to the opening in a manner that the first and second chips protrude from the opposing sides toward each other to leave a gap between the first and second chips, with the gap being smaller in dimension than the opening, allowing bond pads formed on the active surfaces of the first and second chips to be exposed to the opening of the substrate; at least a third chip having an active surface and a non-active surface opposed to the active surface, wherein the active surface of the third chip is mounted on the non-active surfaces of the first and second chips and over the gap, and bond pads formed on the active surface of the third chip are exposed to the gap; a plurality of first bonding wires for electrically connecting the third chip to the first and second chips; a plurality of second bonding wires for electrically connecting the first and second chips to the lower surface of the substrate, a plurality of third bonding wires for electrically connecting the third chip to the lower surface of the substrate; a first encapsulant formed on the upper surface of the

Affiliated with

Also associated with

Rating

Window-type multi-chip semiconductor package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Window-type multi-chip semiconductor package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Window-type multi-chip semiconductor package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3237483