Window-addressable memory circuit

Details Window-addressable memory circuit Window-addressable memory circuit

1983-07-21

1986-12-02

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 702

Patent

active

046270248

ABSTRACT:
A memory circuit in which are stored multiple sets of upper and lower limits that are simultaneously compared with a stream of input data words. The data words and the upper and lower limits may be selectively segmented into data fields or dimensions, and match signals are generated if the input data fields fall within the corresponding fields of the upper and lower limits. The match signals may be selectively masked by a window enable register, and the data fields selected by changing a field length control register.

REFERENCES:
patent: 3931612 (1976-01-01), Stevens et al.
patent: 4473081 (1984-09-01), Dioguardi et al.

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