Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
2000-09-18
2004-02-17
Tse, Young T. (Department: 2634)
Pulse or digital communications
Receivers
Angle modulation
C375S327000, C375S332000, C329S304000
Reexamination Certificate
active
06693980
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to mixing circuits and methods, particularly for receivers handling fast-hopping frequencies.
2. Description of the Related Art
Many modern communications systems employ the concept of “frequency hopping”, in which the frequency of a transmitted signal is changed at a rapid rate. This requires the receiver in such a system to have a wide bandwidth, and to be able to tune to a new frequency quickly and accurately.
One type of front-end used in such a frequency-hopping receiver is shown in
FIG. 1. A
pair of mixers
10
and
11
receive an incoming radio frequency (RF) signal RF
in
at respective first inputs, and local oscillator (LO) signals
12
and
13
at respective second inputs; LO signals
12
and
13
are separated in phase by 90°. Mixers
10
and
11
produce respective outputs which contain components derived from the sum of and the difference between the mixer's input signals. The outputs of mixers
10
and
11
are typically passed through respective low-pass filters
14
and
16
to remove the sum components. The filtered output of mixer
10
is passed through another 90° phase shifter
18
, and the outputs of shifter
18
and mixer
11
are added together using a summing circuit
20
to produce an intermediate frequency (IF) output IF
out
. The 90° between LO signals and the 90° phase shift provided by phase shifter
18
are used to suppress response at the “image” frequency, which is given by LO−IF when RF>LO and RF−LO=IF, and given by LO+IF when RF<LO and LO−RF=IF.
The front-end is tuned to a specific RF frequency by providing LO signals of the appropriate frequency. Conventionally, the LO signals are provided by a low phase noise phase-locked loop (PLL) circuit
24
, which receives a fixed input frequency f
crystal
and multiplies it up to the necessary LO frequency. To accommodate different incoming RF frequencies, PLL
24
typically includes a divide-by-N counter
26
in its loop. The value of N is made changeable by means of a digital command, with different LO frequencies provided by commanding different N values. The PLL output sin &ohgr;
LO
t is passed through a 90° phase shifter
28
to provide a signal cos &ohgr;
LO
t, and both sin &ohgr;
LO
t and cos &ohgr;
LO
t are passed through respective squaring circuits
30
and
32
to provide the quadrature LO signals
13
and
12
, respectively.
Unfortunately, a PLL is ill-suited for use in a wideband receiver which must accommodate rapid frequency hopping. The 0° and 90° LO signals are typically generated using either a ring oscillator VCO that produces quadrature outputs, or (as shown in
FIG. 1
) an LC-VCO whose output goes through a 90° phase shift network. Both of these approaches are inherently narrowband, however, and do not accommodate image rejection over a wide bandwidth as is required by current and future wireless communications systems. Additionally, the acquisition settling time of a wideband, low phase noise PLL is on the order of microseconds, which may be too slow to accommodate fast-hopping hopping schemes.
SUMMARY OF THE INVENTION
A wideband fast-hopping receiver front-end and mixing method are presented which overcome the problems noted above, providing a wideband RF receiver front-end with extremely fast frequency hopping capability.
Direct digital synthesis (DDS) is used to provide the quadrature LO signals to the front-end's mixers. DDS circuits operate by storing one or more sequences of digital words, each of which represents a desired waveform. In response to a clock signal and a command signal, a sequence is output to a digital-to-analog converter (DAC), which converts the digital word sequence to the desired waveform. In the present application, a DDS circuit stores pairs of digital word sequences; one sequence of each pair corresponds to the in-phase LO signal and the other sequence corresponds to the quadrature LO signal. Each stored sequence pair represents in-phase and quadrature LO signals at a particular frequency, and a particular pair of sequences is output to the DACs in response to the clock signal, which is preferably generated with a narrowband PLL, and the command signal. Frequency hopping is accomplished by changing the command signal, which causes a different pair of sequences to be output and the frequency of the LO signals provided to the mixers to be changed. The described method of generating quadrature LO signals is inherently wideband, and provides reduced phase noise in comparison with PLL-based circuits, due to the fixed DDS clock frequency generated by the narrowband PLL. Phase noise of the DACs is limited only by the process technology used (preferably bipolar). Furthermore, the settling time of a DDS circuit is several orders of magnitude less than for a PLL, such that the present invention provides much faster frequency-hopping capability which lends itself to a monolithic solution.
Active image rejection is preferably combined with the DDS LO generation to provide faster frequency hopping. The front-end can be combined with an analog-to-digital converter (ADC) and a communications signal processor to provide a complete system, all of which can be integrated together on a common substrate.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.
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Devendorf Don C.
Linder Lloyd F.
Morrison & Foerster / LLP
TelASIC Communications, Inc.
Tse Young T.
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