Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-10-13
2001-10-23
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C375S376000
Reexamination Certificate
active
06307411
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to an apparatus and method for a wide tracking range phase lock loop (“PLL”) with exceptionally low jitter. In particular, the present invention relates to PLL applications that require low phase noise or zero crossing jitter for encoded transmissions. A PLL of the present invention separates the clock from the encoded data such that the recovered clock and data are both reduced significantly in jitter. This is very helpful in accurate position control applications that require precise phase, spatial or time measurement or control.
BACKGROUND OF THE INVENTION
It is often necessary in communication, digital audio and similar applications to lock to an external clock or reference while generating a new clock source that is immune to various sources of phase and frequency noise in the incoming reference signal. In order for a receiver to receive and capture data, as referenced to a transmitter's clock signal, it is necessary for the receiver to have a clock signal that is synchronized or phase aligned to the same clock signal.
Phase locked loop (PLL) circuits have been commonly used for the purpose of generating a signal in a preferred phase relationship relative to another signal. A PLL carefully adjusts to its own clock (the “local oscillator”) to bring it into precise alignment with some external signal (the “reference clock”). In serial data communications and similar applications, the reference clock is often embedded in a stream of data bits. It is the PLL's task in a clock recovery subsystem to align its local oscillator with the reference clock information embedded in the data stream. The PLL circuit within the receiver can adjust its local clock signal frequency to a multiple of the reference signal frequency, thereby phase aligning the two signals together. The phase relationship between the reference signal and the local clock signal is then referred to as being locked. Once properly aligned, the local oscillator can be used to clock bits out of the data stream, sampling each data baud right in the center at the point of maximum noise immunity.
As illustrated in
FIG. 1
, a conventional PLL
10
provides a feedback system combining a voltage-controlled oscillator (VCO)
12
and a phase comparator or detector
14
in electronic communication therewith such that the oscillator frequency or phase accurately tracks that of an applied frequency or phase-modulated signal, respectively. In a PLL, the error signal from the phase comparator is the difference between the input frequency or phase and that of the signal fed back. If f
in
does not equal f
VCO
, phase comparator
14
generates a phase error output signal that is a measure of the phase difference. The phase error signal, after being filtered by loop filter
16
and amplified by amplifier
18
, causes f
VCO
to deviate in the direction of f
in
. The VCO will eventually “lock” to f
in
so as to maintain a fixed relationship with the input signal.
In this application, any imperfections in a transmit clock that is used to construct a data stream may compromise the ability of the PLL to properly align its local oscillator. Imperfections in the transmit clock are sometimes classified as frequency offsets, wander or, as used herein, “jitter”. Jitter, a common problem associated with PLL circuits, can be defined as abrupt, spurious variations in the phase of successive pulses as referenced to the phase of a continuous oscillator, causing deleterious variations in the output frequency. As the jitter frequency on the input signal increases, the bandwidth requirements of the PLL likewise increase. The precision of the recovered clock, therefore, is a limitation on system performance.
With the introduction of more sophisticated services involving the transfer of large amounts of information such as digital data, video or voice data, communication networks must provide predictably superior levels of performance while ensuring the maintenance of data quality. In a digital communication system, for instance, one application of a PLL may be to provide a “clean” clock signal which has the same frequency and phase as a received digital data signal that is to be decoded. A typical digital PLL design uses a reference clock having a frequency that is much higher than that of an incoming data signal to generate the output clock. This approach, however, can only guarantee a phase lock that is within one clock period of the reference clock. This error in the phase lock constitutes jitter. In analog conventional PLL circuits jitter is commonly caused by the errors in the filtering of the control voltage and VCO noise.
Once jitter contaminates a signal, it propagates through a system, often increasing as it passes through various devices. PLLs have therefore traditionally found limited use in those systems requiring very high stability. Systems incorporating radar oscillators, for example, require very high stability that can only be provided by narrowing the loop bandwidth. This in turn degrades the frequency tracking performance of the PLL and detracts from an inherently desirable feature of PLL oscillators. When the loop gain of the PLL is high, the pull-in and lock-in times are short, yet the sensitivity to noise (both internal and external) becomes high, resulting in large phase jitter and frequency jitter in the output. On the other hand, when the loop gain of the PLL is low and the bandwidth is narrow so as to remove noise, the pull-in and lock-in capabilities for the frequency offset and the initial phase difference become low, resulting in narrower pull-in and lock-in ranges. The narrow bandwidth of the loop not only takes a long time to achieve the lock-in state for a large frequency offset but also presents difficulty in holding the lock-in state for a frequency shift. It therefore becomes difficult for the loop to lock, and track and carrier loss is realized.
It is therefore desirable to construct a low jitter PLL that has a relatively large bandwidth by controlling harmonics that creep in at higher bandwidths. Good harmonic suppression is important in PLLs because this affects loop characteristics (i.e., stability, phase error, jitter). Although not readily apparent, harmonics with balanced codes exist off of the fundamental that can cause false locks with pseudo-random code streams. A PLL that exhibits optimum harmonic suppression is therefore not only beneficial in reducing jitter on the transmit side, but it is also instrumental in rejecting noise and transmission-media-induced distortions on both of the reception and instrumentation sides.
SUMMARY OF THE INVENTION
The present invention provides a wide tracking range phase locked loop (PLL) circuit that achieves minimal jitter in a recovered clock signal. The PLL of the present invention is particularly adapted for applications that require excellent stability (i.e., low phase noise and/or low phase drift). The PLL of the present invention is further applicable for encoded transmissions containing clock and/or data such that the recovery of such clock and/or data is effected without the need for signal acquisition preambles, while avoiding harmonic locks in fixed and/or swept frequency systems.
The PLL circuitry disclosed herein provides a means to produce a low jitter recovered clock regardless of the source of the jitter (i.e. whether it is in the source or the transmission media) and has automatic harmonic lockout detection circuitry through means of a novel lock and seek control logic in electrical communication with a programmable frequency discriminator and a code balance detector. The frequency discriminator enables preset of a frequency window of upper and lower frequency limits to derive a programmable range within which signal acquisition is effected. The discriminator works in combination with the code balance detector circuit to minimize the potential for false lock. Useable frequency sweeps may thereby extend through several frequency harmonics while avoiding such harmonics during signal acquisit
Bogosian Margaret C.
Brookhaven Science Associates
Nguyen Linh
Wells Kenneth B.
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