Wide neck shallow trench isolation region to prevent strain...

Details Wide neck shallow trench isolation region to prevent strain... Wide neck shallow trench isolation region to prevent strain...

2005-05-24

2005-05-24

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S427000, C438S585000

Reexamination Certificate

active

06897122

ABSTRACT:
The present invention enables the production of improved high-speed semiconductor devices. The present invention provides the higher speed offered by strained silicon technology coupled with the smaller overall device size provided by shallow trench isolation technology without relaxation of the portion of the strained silicon layer adjacent to a shallow trench isolation region by laterally extending a shallow trench isolation into the strained silicon layer overlying a silicon germanium layer.

REFERENCES:
patent: 6355538 (2002-03-01), Tseng
patent: 6787423 (2004-09-01), Xiang
patent: 6828248 (2004-12-01), Tao et al.
patent: 20030049893 (2003-03-01), Currie et al.

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