Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-12-09
2004-02-24
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S426000, C438S427000, C438S435000, C438S301000, C438S585000
Reexamination Certificate
active
06696348
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacturing of semiconductor devices, and more particularly, to forming strained-silicon devices with improved electrical characteristics.
BACKGROUND OF THE INVENTION
An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing power consumption in semiconductor devices. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFET) are particularly well suited for use in high-density integrated circuits. As the size of MOSFET and other devices decrease, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
Strained silicon transistors provide increased semiconductor performance with decreased power consumption. Strained silicon transistors are created by depositing a layer of silicon germanium (SiGe) on a bulk silicon wafer. A thin layer of silicon is subsequently deposited on the SiGe layer. The distance between atoms in a SiGe crystal lattice is greater than the distance between atoms in an ordinary silicon crystal lattice. There is a natural tendency of atoms inside different types of crystals to align with-one another where one crystal is formed on another crystal. As such, when a crystal lattice of silicon if formed on top of a layer of SiGe, the atoms in the silicon crystal lattice stretch or “strain” to align with atoms in the SiGe lattice. A resulting advantage of such feature is that the strained silicon experiences less resistance to electron flow and produces gains of up to 80% in speed as compared to ordinary crystalline silicon.
Shallow trench isolation (STI) provides another technique to shrink device size. The use of STI significantly shrinks the area needed to isolate transistors better than local oxidation of silicon (LOCOS). STI also provides superior latch-up immunity, smaller channel width encroachment, and better planarity. The use of STI techniques eliminates the bird's-beak frequently encountered with LOCOS.
Strained silicon layers are typically epitaxial layers formed by chemical vapor deposition (CVD) to a thickness of about 100 Å to about 300 Å. The thickness of the strained silicon layer depends on the Ge concentration in the SiGe layer. The critical thickness of a strained silicon layer is the maximum thickness below which the strained silicon is defect free. At thicknesses above the critical thickness, the strained silicon layer tends to relax, the crystalline geometry of the relaxed region becoming more like ordinary crystalline silicon and less like a SiGe crystal. When the Ge concentration in the SiGe layer is about 15%, the critical thickness of the strained silicon layer is about 300 Å. When the Ge concentration in the SiGe layer is about 20%, the critical thickness of the strained silicon layer is about 200 Å. When the Ge concentration in the SiGe layer is about 30%, the critical thickness of the strained silicon layer is about 100 Å.
Strained silicon layers also tend to relax in the portion of a strained silicon layer adjacent to the boundary of a strained silicon layer and an STI region trench sidewall. A semiconductor device
50
as shown in
FIG. 1
, comprises a strained silicon layer
16
formed overlying a SiGe layer
14
on a silicon-containing substrate
12
. An STI region
48
with a trench sidewall
52
borders the strained silicon layer
16
and the SiGe layer
14
. A gate oxide layer
36
and polysilicon gate electrode layer
38
are formed overlying the strained silicon layer
16
. The portion of the strained silicon layer
42
adjacent STI region trench sidewall
52
tends to relax, becoming more like ordinary crystalline silicon. As a result of strained silicon relaxation, electrons move slower through the portion of the strained silicon region adjacent a STI region
42
than through the remaining portion of the strained silicon layer not adjacent to the STI region
46
.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.
SUMMARY OF THE INVENTION
There exists a need in the semiconductor device art for a device that combines the performance improvements of strained silicon technology and STI technology. There exists a need in this art to produce a semiconductor device without relaxation of the portion of the strained silicon layer adjacent to a STI region trench sidewall.
These needs are met by a semiconductor device comprising a silicon-containing substrate with a silicon germanium (SiGe) layer formed on the silicon-containing substrate. A strained silicon layer is formed on the SiGe layer. A trench isolation region is formed extending into the strained silicon layer and the SiGe layer, wherein the portion of the isolation region in the strained silicon layer has a greater width than the portion of the isolation region in the SiGe layer.
The earlier stated needs are also met by a method of forming a semiconductor device comprising forming a SiGe layer on a silicon-containing semiconductor substrate. A silicon layer is formed over the SiGe layer. A layer of a first insulating material is formed on the SiGe layer and a layer of a second insulating material is formed on the first insulating material layer. A trench of a first. width is formed in the layer of first insulating material and the layer of the second insulating material. The trench is extended into the silicon layer in both the lateral and vertical directions, so that the trench undercuts the layer of first insulating material. The trench formed in the first and second insulating layers is further extended into the SiGe layer such that a portion of the trench extending into the SiGe layer has substantially the same width as the first width. The trench is filled with an insulating material.
The earlier stated needs are further met by a method of forming a semiconductor device comprising forming a SiGe layer on a silicon-containing semiconductor substrate. A silicon layer is formed over the SiGe layer. A trench of a first width is formed in the silicon layer exposing the SiGe layer. An opening is formed in the SiGe layer in the trench, wherein the opening has a second width that is less than the first width. The opening and the trench are filled with an insulating material to form an isolation region.
This invention addresses the needs for an improved high-speed semiconductor device comprising strained silicon technology and STI technology without relaxation of the portion of the strained silicon layer adjacent the STI region.
The foregoing and other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6355538 (2002-03-01), Tseng
patent: 2003/0049893 (2003-03-01), Currie et al.
Advanced Micro Devices , Inc.
Chen Jack
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