Boots – shoes – and leggings
Patent
1992-12-18
1995-05-23
McElheny, Jr., Donald E.
Boots, shoes, and leggings
36423221, 3642329, G06F 900
Patent
active
054189756
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The invention relates to computing technology, more specifically to the central processors of computing systems. It can be used for scientific-technical and economic-statistical computations, the tasks of automation of designing, modelling and control.
PRIOR ART
Known in the art is a central processor usable in a computing system comprising arithmetical devices for performing operations over integers and the numbers with a floating point, which are controlled by an extended control work in each machine cycle. The processor comprises also register files, an arithmeticologic device of integral and floating arithmetics, a block of registers of presentation of information into a memory, a mathematical-to-physical-address-conversion block.
For storing a program in the central processor there is provided a buffer memory in which a command is stored in unpacked form (IEEE Transactions on computers, v.37, No.8, 1988, Robert P. Colwell, Robert P. Nix, John J. O. Donnel, David B. Papworth, Paul K. Rodman, AVLIW Architecture for a Trace Scheduling Compiler, p. 967-979).
Such a processor has the architecture of an extended control work and its efficiency depends to a lesser degree on the nature of calculations, both scalar and/or vector ones.
However, this processor is designed mainly for the solution of tasks of numerical analysis with well predicted transfer direction or with the absence of prediction, its efficiency is markedly reduced. Parallelism in operation on the cyclic portions of a program is attained by unrolling the cycles, which results in an increase in a code size and the lack of a possible code compacting on the boundaries between the unrolled cycles.
Known is a central processor usable in a computing system for scientific-technical, economic-statistical computation, the tasks of automation of designing, modelling and control with the architecture of an extended control word, which assures high efficiency both on vector and scalar computations and comprising an interface device coupling the central processor with an exchange bus with a common internal storage, a multi-channel arithmeticologic device permitting performing operations in conditional and unconditional cycles, a data commutator connecting the input of the arithmeticologic device with its output and with a data buffer memory comprising a plurality of the last procedure activations and a subset of element arrays preloaded for a subsequent processing in the cycle. The processor also contains a memory for storing data lacking in the data buffer memory, a call-recording device contributing to producing scalar addresses, and a multi-channel indexing device assuring the production of vector addresses for exchange with the common internal storage via a mathematical-to-physical address-conversion device, realizing additionally for the vectors the preliminary call of a line of the next mathematical page a subprogram device realizing the preparation of an address context, calling of a new program code and procedure switching without stopping a command decoder coupled with an associative memory and with the control means. For ensuring the parallel start of the arithmeticologic device, the call-recording device and multichannel indexing device and preparation of transfer command, provision is made of a control device also connected to the data buffer memory and the subprogram device.
The processor also comprises a command buffer memory with a control means storing a current working set of procedures (PCT/SU 90/00134).
DISCLOSURE OF THE INVENTION
However, when the initial operands usable in a command have not yet been read from the internal storage, blocking in a conventional device is formed with delay, which results in time losses because of a necessity to repeat the commands recorded after the disabled instruction.
It is the principal object of the present invention to provide a central processor with the architecture of and extended instruction word which would increase the efficiency of scalar and vector calculations on
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Babaian Boris A.
Gorshtein Valery Y.
Kim Alexandr K.
Nazarov Leonid N.
Sakhin July K.
Institut Tochnoi Mekhaniki I Vychislitelnoi Tekhniki Imeni S.A.
McElheny Jr. Donald E.
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