Wide frequency-range delay-locked loop circuit

Details Wide frequency-range delay-locked loop circuit Wide frequency-range delay-locked loop circuit

2000-05-17

2001-12-04

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000, C327S048000, C327S040000

Reexamination Certificate

active

06326826

ABSTRACT:

BACKGROUND
1. Technical Field
This invention relates to delayed-locked loops.
2. Description of the Related Art
Skew reduction techniques using a phase-locked loop (PLL) or delay-locked loop (DLL) have become increasingly important as the required system bandwidth increases. Especially, the DLL has become more popular as a zero delay buffer because of its better stability and better jitter characteristics than the PLL. However, the conventional DLL does not offer a frequency range as wide as the PLL does because of its inherent limitation on the frequency range and the problem of false locking. PLLs and DLLs are typically used in synchronous systems wherein the integrated circuits in the system are synchronized to a common reference clock.
In the phase-locked loop, a voltage-controlled oscillator produces a local clock. The phases of the local clock and a reference clock are compared by a phase-frequency detector, with the resulting error signal used to drive the voltage-controlled oscillator via a loop filter. The feedback via the loop filter phase locks the local clock to the reference clock. Stability of the feedback loop, however, depends in part on the loop filter. The electronic characteristics of the loop filter, in turn, often depend significantly on manufacturing parameters. As a result, the same loop filter design may result in a stable feedback loop when manufactured with one process but an unstable loop when manufactured by another. It is difficult to produce a single loop filter design for use with all manufacturing processes, and the design of the loop filter typically must be optimized on a process by process basis.
The delay-locked loop generates a synchronized local clock by delaying the incoming reference clock by an integer number of periods. This approach avoids the stability problem inherent in the phase-locked loop approach. Delay-locked loops, however, have a disadvantage of narrow frequency range. The delay-locked loop adjusts the amount of additional delay in order to achieve the desired synchronization, but this adjustment is essentially a phase adjustment. The conventional delay-locked loop lacks any significant frequency adjustment, thus limiting the overall frequency range of conventional delay-locked loops. Furthermore, delay-locked loops may falsely lock on a frequency.
Accordingly, it is desirable to achieve a delay-locked loop that can operate over a wide frequency range and which can provide protection against false locking.
SUMMARY
The present invention provides a DLL that is operable over a wide frequency range, and that provides protection against false locking.
The DLL in accordance with the present invention generates a set of multiphase clocks whose delays are locked to an input reference signal. In one embodiment, the DLL includes a plurality of delay elements adapted to incrementally delaying the input reference clock to generate a set of multi-phase clocks, frequency detector logic adapted to counting the number of rising edges occurring on the set of multi-phase clocks in one period of the input reference clock and a loop filter adapted to generating a control signal to adjust the delay amount of each delay element when the number of rising edges is different from a predetermined number. The predetermined number can be set by the number of the delay elements minus one. The process of locking to the frequency of the input reference clock by comparing the number of rising edges with the predetermined number prevents false locking that occurs when the delay time through the delay chain is a multiple of the reference clock period, in which case the numbers would not match.


REFERENCES:
patent: 4316150 (1982-02-01), Crosby
patent: 4378509 (1983-03-01), Hatchet et al.
patent: 4424497 (1984-01-01), Fellinger
patent: 4779008 (1988-10-01), Kessels
patent: 4820993 (1989-04-01), Cohen et al.
patent: 4970475 (1990-11-01), Gillig
patent: 5101117 (1992-03-01), Johnson et al.
patent: 5109394 (1992-04-01), Hjerpe et al.
patent: 5233314 (1993-08-01), McDermott et al.
patent: 5274281 (1993-12-01), Hay
patent: 5317283 (1994-05-01), Korhonen
patent: 5373255 (1994-12-01), Bray et al.
patent: 5436596 (1995-07-01), Folmer
patent: 5511100 (1996-04-01), Lundberg et al.
patent: 5552726 (1996-09-01), Wichman et al.
patent: 5592110 (1997-01-01), Noguchi
patent: 5699020 (1997-12-01), Jefferson
patent: 5744991 (1998-04-01), Jefferson et al.
patent: 5815041 (1998-09-01), Lee et al.
patent: 5896066 (1999-04-01), Katayama et al.
patent: 5920214 (1999-07-01), Lee et al.
patent: 5969552 (1999-10-01), Lee et al.
patent: 5987085 (1999-11-01), Anderson
patent: 0 704 975 A1 (1995-09-01), None
T. H. Lee et al., “a 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM”, IEEE Journal of Solid-State Circuits, vol. 29, No. 12, pp. 1491-1496, Dec. 1994.
S. Sidiropoulos et al., “A Semidigital Dual Delay-Locked Loop”, IEEE Journal of Solid State Circuits, vol. 32, No. 11, pp. 1683-1692, Nov. 1997.
S. Tanoi, et al., “A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture”, IEICE Trans. Electron, vol. E79-C, No. 7, Jul. 1996, pp. 898-904.
C. H. Coleman, “A New Technique for Time-Base Stabilization of Video Recorders”, IEEE Transactions on Broadcasting, vol. BC-17, No. 1, Mar. 1971, pp. 29-36.
J. G. Maneatis, “Low-Jitter and Process-Independent DLL and PLL Based On Self-Biased Techniques”, IEEE International Solid State Circuits Conference, Feb. 1996, pp. 130-131, 430.

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