Wide dynamic range delta sigma analog-to-digital converter with

Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder

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341139, H03M 302

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active

052413101

ABSTRACT:
A delta sigma analog-to-digital architecture assures that all channels in a multi-element receiver follow the same compression and/or time-gain variation curve. This is accomplished by varying the reference voltage as a function of time so that the full scale range and associated quantization noise are large at the beginning of the receiving interval and become smaller as more distant echoes arrive. All channels follow the identical gain curve since all channels have the same reference voltage at the same time. The distribution of time-varying reference voltages may be done by using analog buses or by employing a timevarying digital code that specifies the reference voltages derived from a digital-to-analog (D/A) converter. In the latter case, corrections can be applied to the code at each channel.

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patent: 5084702 (1992-01-01), Ribner
patent: 5103229 (1992-04-01), Ribner
Hurst et al., "Delta-Signa A/Ds With Reduced Sensitivity To Op Amp Noise," IEEE Proc. ISCAS '89, pp. 254-257, May 1989.
Hauser et al., "MOS ADC-Filter Combination That Does Not Require Precision Analog Components", ISSCC Dig. Tech. Pap., pp. 80-81, 313, Feb. 1985.
J. C. Candy, "A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital Converters", IEEE Transactions on Communications, vol. COM-22, No. 3, Mar. 1974, pp. 298-305.
J. C. Candy et al., "Using Triangularly Weighted Interpolation to get 13-Bit PCM from a Sigma-Delta Modulator", IEEE Transactions on Communications, vol. COM-24, No. 11, Nov. 1976, pp. 1268-1275.
J. C. Candy, "A Use of Double Integration in Sigma Delta Modulation", IEEE Transactions on Communications, vol. COM-33, No. 3, Mar. 1985, pp. 249-258.

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