Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1989-07-19
1991-12-31
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
328133, 307511, 331 25, 375118, 375120, H03D 324, H03K 513
Patent
active
050775294
ABSTRACT:
A device (16) for reducing the intrinsic low frequency jitter within a Digital Phase lock loop (17). A Digital Phase lock loop high speed clock signal (4) is produced by a multistage oscillator (5), producing a plurality of identical frequency signals, each differing in phase. An adjust signal (18) generated by the Digital Phase lock loop output clock signal (3) causes an adjacent phase angle to be selected as the high speed clock signal (4), thereby reducing the period of the clock signal (4) and, in effect, accelerating the high speed clock signal (4). The current state of the selected phase and the appropriate selection of adjacent phase is monitored by a ten stage shift register (20-29), the presence of a "high bit" within a particular shift register block causing selection of the individual phase (6-15) which serves as the input to that particular shift register stage. An error correction circuit (40) detects the presence of more or less than a single high bit within the shift register stages (20- 29).
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C. Shih and S. Sun, "Jitter Attenuation Phase Lock Loop Using Switched Capacitor Controlled Crystal Oscillator", Proceedings of the IEEE 1988.
Ghoshal Sajol C.
Ray Daniel L.
Cunningham Terry D.
Level One Communications Inc.
Miller Stanley D.
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