Wide bandwidth bias tee

Details Wide bandwidth bias tee Wide bandwidth bias tee

2002-02-01

2003-12-02

Ham, Seungsook (Department: 2817)

Wave transmission lines and networks

Long line elements and components

C333S172000, C333S185000

Reexamination Certificate

active

06657522

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of signal transmission, and more particularly to a bias tee for inserting low frequency signals on high frequency transmission lines.
BACKGROUND OF THE INVENTION
Bias tees are widely used to insert low frequency (e.g., DC) signals onto high frequency (e.g., radio frequency (RF)) lines.
FIG. 1
shows a schematic diagram of a conventional bias tee
100
. The bias tee
100
includes a high frequency input terminal
110
and a low frequency input terminal
120
. The bias tee
100
also includes a first resistor (R
1
)
135
coupled between the high frequency input terminal
110
and ground, and a series-connected capacitor (C
1
)
140
and second resistor (R
2
)
150
coupled between the high frequency input terminal
110
and ground.
In operation, a high frequency (e.g., RF) transmission line (not shown) is coupled to the high frequency input terminal
110
and a low frequency (e.g., DC) signal (not shown) is applied at the low frequency input terminal
120
. It will be noted by those skilled in the art that the high frequency signal (not shown) present on the high frequency transmission line is grounded through first resistor
135
. Additionally, the high frequency signal is prevented from reaching the low frequency input terminal
120
by the first capacitor
140
and the second resistor
150
. As is well known in the art, the first capacitor
140
will operate as a virtual short circuit with respect to high frequency signals, thereby shunting all such signals to ground through the second resistor
150
. The low frequency signal applied at low frequency input terminal
120
however will pass through to the high frequency transmission line coupled to the high frequency input terminal
110
(since first capacitor
140
operates as an open circuit with respect to the low frequency signal). In this manner, a DC bias signal may be carried on the high frequency transmission line along with the high frequency signal.
However, in the bias tee
100
shown in
FIG. 1
, a high frequency signal which is present at high frequency input terminal
110
must pass through both the capacitor
140
and the second resistor
150
before reaching ground which increases the total impedance to ground. Furthermore, when the bias tee is formed monolithically, the high frequency signal must pass through a via between the first capacitor
140
and ground formed on a lower surface of the monolithic substrate (e.g., glass). Since the diameter of the via is typically small, the via exhibits a high inductance, and therefore limits the bandwidth of the bias tee
100
. It will be noted by those of ordinary skill in the art that a wide bandwidth is necessary for almost all high frequency applications.
Therefore, there is presently a need for a wide bandwidth bias tee.
SUMMARY OF THE INVENTION
The present invention includes a wide bandwidth bias tee including a high frequency terminal, a first resistor coupled between the high frequency terminal and a capacitor, a second resistor coupled to the capacitor, the second resistor coupled in series with the first resistor, and a low frequency terminal, the low frequency terminal coupled to the second resistor.
The present invention also includes an integrated circuit bias tee comprising a substrate including a grounding pedestal layer formed therein, a capacitor plate structure disposed on the grounding pedestal layer, at least one first resistor formed on a first side of the capacitor plate structure and coupled thereto, and at least one second resistor formed on a second opposing side of the capacitor plate structure and coupled thereto.
Additionally, the present invention comprises a method for increasing the bandwidth of a bias tee including, disposing a capacitor of the bias tee on a first surface of a monolithic substrate and disposing a ground pedestal in the monolithic substrate and coupling a plate of the capacitor directly thereto.


REFERENCES:
patent: 5105172 (1992-04-01), Khatibzadeh et al.
patent: 5241284 (1993-08-01), Nyqvist et al.
patent: 5495180 (1996-02-01), Huang et al.
patent: 5760662 (1998-06-01), Kalb et al.
patent: 6273400 (2001-08-01), Kuchta
patent: 6285542 (2001-09-01), Kennedy et al.

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