Amplifiers – With semiconductor amplifying device – Including balanced to unbalanced circuits and vice versa
Reexamination Certificate
2001-03-30
2003-05-20
Tokar, Michael (Department: 2819)
Amplifiers
With semiconductor amplifying device
Including balanced to unbalanced circuits and vice versa
C330S253000, C330S257000
Reexamination Certificate
active
06566961
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to single-ended to differential converters, and more particularly to wide-band single-ended to differential converters (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively, using CMOS technology.
2. Description of the Related Art
FIG. 1
shows the prior art of a single to differential circuit which is directly derived from its bipolar counterpart, while
FIG. 3
is the small signal version of FIG.
1
. However, it is observed (and will be shown later) that the performance of this circuit cannot meet the requirement for a wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively, using CMOS technology, especially at high frequencies.
FIG. 1
is a differential amplifier comprised of transistors M
1
and M
2
, their sources are coupled to a reference potential via a tail current source transistor M
3
. Their drains are coupled each to a voltage supply V
DD
via resistive means R
L1
. The gate of M
1
is connected to input INP via capacitive means C
I1
. Input VBIAS
1
provides bias to the gates of M
1
and M
2
via resistive means R
B1
and R
B2
, respectively. The gate of M
2
is also connected to a reference potential via capacitive means C
I2
. VBIAS
2
provides bias to the gate of M
3
. Outputs OUTA and OUTB are coupled to the drains of M
1
and M
2
, respectively.
FIG. 3
, which shows parasitic gate-source capacitances C
A
and parasitic tail current capacitance C
B
will be discussed in detail in the Description of the Preferred Embodiment, because it directly bears on the design of the present invention.
Another prior art of a differential amplifier with capacitors for cancellation of the negative feedback action of the gate to drain parasitic capacitance C
GD
at high frequencies is explained in Alan B. Grebene, “
Bipolar and MOS Analog Integrated Circuit Design
”, John Wiley and Sons, 1991, pp 415-416. This second prior art, however, does nothing to improve the amplitude and phase imbalances that we are concerned with.
The following US Patents relate to single-ended to differential converters:
1. U.S. Pat. No. 4,292,597 (Nimura et al.) Circuit for Converting Single-Ended Input Signals to a Pair of Differential Output Signals.
2. U.S. Pat. No. 4,369,411 (Nimura et al.) Circuit for Converting Single-Ended Input Signals to a Pair of Differential Output Signals.
3. U.S. Pat. No. 5,068,621 (Hayward et al.) Compensation Method and Apparatus for Enhancing Single Ended to Differential Conversion.
4. U.S. Pat. No. 5,220,286 (Nadeem) Single Ended to Fully Differential Converters, describes single-ended to differential converters using switched capacitor circuits. It is well known that the highest frequencies that can be handled by such circuits are in the range of a few hundreds of Kilohertz only.
5. U.S. Pat. No. 5,614,864 (Stubbe et al.) Single-Ended to Differential Converter with Relaxed Common-Mode Input Requirements.
6. U.S. Pat. No. 5,805,019 (Shin) Voltage Gain Amplifier for Converting a Single Input to a Differential Output, discloses single-ended to differential converters using switched capacitor circuits. It is well known that the highest frequencies that can be handled by such circuits are in the range of a few hundreds of Kilohertz only.
7. U.S. Pat. No. 5,896,053 (Prentice) Single Ended to Differential Converter and 50% Duty Cycle Signal Generator and Method, describes a circuit that can operate up to 300 MHz. But the implementation is with bipolar devices and is quite different from the invention described.
8. EP 0766381 (Stubbe et al.) Improved Single-Ended to Differential Converter with Relaxed Common-Mode Input Requirements, similar to U.S. Pat. No. 5,614,864 (Stubbe et al.) above.
9. EP 0472340 (Hayward et al.) A Compensation Method and Apparatus for Enhancing Single Ended to Differential Conversion, similar to U.S. Pat. No. 5,068,621 (Hayward et al.) above.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide circuits and a method for a wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively, using CMOS technology.
These and many other objects have been achieved by the use of capacitive means C
D
across the gate and source of first stage MOS transistor M
1
with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage. Using equal valued capacitive means C
F1
, C
F2
in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.
In the following, first and second conductivity types are opposite conductivity types, such as N and P types. Each embodiment includes its complement as well.
REFERENCES:
patent: 3932768 (1976-01-01), Takahashi et al.
patent: 4292597 (1981-09-01), Niimura et al.
patent: 4369411 (1983-01-01), Niimura et al.
patent: 5068621 (1991-11-01), Hayward et al.
patent: 5220286 (1993-06-01), Nadeem
patent: 5404050 (1995-04-01), Nauta
patent: 5614864 (1997-03-01), Stubbe et al.
patent: 5805019 (1998-09-01), Shin
patent: 5896053 (1999-04-01), Prentice
patent: 6285259 (2001-09-01), Franck et al.
patent: 0472340 (1992-02-01), None
patent: 07663381 (1997-04-01), None
A. Grebene, “Bipolar and MOS Analog Integrated Circuit Design,” John Wiley and Sons, 1991, pp. 415-416.
Dasgupta Uday
Hwee Teo Tian
Ackerman Stephen B.
Institute of Microelectronics
Khai Nguyen
Saile George O.
Tokar Michael
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