Pulse or digital communications – Receivers – Interference or noise reduction
Reexamination Certificate
1998-08-12
2002-10-29
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Interference or noise reduction
C375S285000, C375S349000
Reexamination Certificate
active
06473474
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to providing wide band digital receivers.
2. Description of Related Art
In order to cover a broad frequency band, channelized architectures are employed. Channelization is the partitioning of the broad frequency bands into channels, so that signals in each channel can be sensed or modulated independent of what is happening to the other channels. Channelization is accomplished with digital filers.
The recent improvements in analog to digital converter clock rates and resolution mean that now wide band widths can be achieved. Likewise, the reduction in cost and increase in circuit density of digital signal processing components means that a practical channelization architecture can be achieved. However, these components are often not compatible with each other for many applications of interest, especially the electronic warfare applications. In particular, the specialized digital signal processing integrated circuits that perform the channelization filtering function cannot operate at as high a clock rate as the analog to digital converters or the digital to analog converters.
This inherent clock rate incompatibility was encountered earlier during the development of present day non-channelized digital RF memories (DRFM). In that case, the problem was that the analog to digital clock converter and the digital to analog converter clock rates were much higher than the clock rates of the memory chips.
Attempted solutions to this problem used demultiplexers and multiplexers to match clock rates. This approach worked because the spectral content of individual sections of memory were of no concern. The only thing that mattered was whether the full signal information could be written into and read out of the digital memory.
However, when used for the intended wide band digital receiver application, the conventional thinking is that demultiplexer and multiplexer operation is incompatible with channelized filtering because of aliasing. If done in real time, the demultiplexer function will lower the clock without changing the input signal frequency. This changes the relationship between the clock rate and the signal frequency components, meaning that the information content no longer satisfies the Nyquist limit criteria. Therefore, the data will include the input signal accompanied by false signals known as alias terms because there is insufficient information to describe the true signal unambiguously.
Another approach to solving certain clock rate difference problems is known as “decimation”. Decimation is the selection of certain percentage of the data values, e.g., 1 out of 8 data values. Decimation allows memory and modulation functions to operate at lower clock rates without losing information for some applications, as discussed above. However, decimation is not an option for reducing the clock rate of the channelization filtering circuitry. Decimation of the data stream can only be accomplished after the filter operation, because the Nyquist limit is determined by the channel bandwidth and not the full bandwidth. So decimation can be used for some purposes, but not for the intended channelization filtering.
Another approach to solving clock rate difference problems is to avoid operating in real time. This approach puts the input signal into a buffer memory and then subsequently processes the signal in non-real time. However, the approach requires a detection of the presence of the signal so that signals can be directed to the memory, otherwise the memory would soon overflow. Accordingly, the receiver or receiver memory needs another receiver for assistance, and thus, the channelization implementation problem has not really been solved. Further, the receiver memories need to operate in real time and many receiver operations also need real time operation. Therefore, for many applications, non-real time operation is not a satisfactory solution.
Another approach for solving clock-rate difference problems is the “brute force” approach of faster digital signal processing integrated circuits. High performance analog to digital converters and digital to analog converters have been developed because there are many applications for them, and hence they are produced in large quantities. However, the large front-end development cost for the specialized digital processors needed for these digital filtering applications is difficult to justify because typically they have low-quantity production rates. Further, development of analog to digital convertors and digital to analog converters will continue, so there is a performance moving target.
Thus the dilemma still remains that even if dense circuit processors are designed to economically constitute many channel filters, a wide net input bandwidth results. However, a wide net input bandwidth requires a high clock rate for the channelizing digital filters in order to avoid the alias terms. But the digital processing technology is not compatible with such a high clock rate. The digital filter processing cannot be connected to the input analog to digital converter which is sampling the wide band. If the clock rate of the analog to digital converter is slowed, then the bandwidth is lost, and further, each analog to digital converter and digital to analog converter can no longer support many filtered channels.
Therefore, while the elements needed to meet the desired goals appear to be there individually, the incompatibility of clock rates make the goals achievement impractical.
SUMMARY OF THE PRESENT INVENTION
The present invention is intended to compensate for the clock rate differences between the analog to digital converters and the specialized digital signal processors that perform the channelization filtering and other signal processing functions.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes in modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5640698 (1997-06-01), Shen et al.
patent: 5867479 (1999-02-01), Butash
patent: 5930231 (1999-07-01), Miller et al.
patent: 6085077 (2000-07-01), Fields et al.
patent: 6205133 (2001-03-01), Bexten
Chin Stephen
Fan Chieh M.
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