Wide adder with critical path of three gates

Details Wide adder with critical path of three gates Wide adder with critical path of three gates

2006-01-24

2006-01-24

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06990510

ABSTRACT:
Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.

REFERENCES:
patent: 5327369 (1994-07-01), Ashkenazi
patent: 6373290 (2002-04-01), Forbes
patent: 05-061643 (1993-03-01), None
patent: 06-282417 (1994-10-01), None
patent: 11-353156 (1999-12-01), None
Yee et al “Clock-Delayed Domino for Adder and Combinational Logic Design”, 1996 IEEE, pp. 332-337.

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