Wet etch suitable for creating square cuts in si

Details Wet etch suitable for creating square cuts in si Wet etch suitable for creating square cuts in si

2006-06-02

2009-12-08

Hendricks, Keith D (Department: 1794)

Etching a substrate: processes

Nongaseous phase etching of substrate

Etching inorganic substrate

C216S099000, C216S103000, C216S096000

Reexamination Certificate

active

07628932

ABSTRACT:
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.

REFERENCES:
patent: 4531282 (1985-07-01), Sakai et al.
patent: 4891255 (1990-01-01), Ciarlo
patent: 5427975 (1995-06-01), Sparks et al.
patent: 5536675 (1996-07-01), Bohr
patent: 6100162 (2000-08-01), Doan et al.
patent: 6245615 (2001-06-01), Noble et al.
patent: 6290863 (2001-09-01), Morgan et al.
patent: 6319333 (2001-11-01), Noble
patent: 6339241 (2002-01-01), Mandelman et al.
patent: 6358861 (2002-03-01), Ohji et al.
patent: 6391793 (2002-05-01), Lee et al.
patent: 6465865 (2002-10-01), Gonzalez
patent: 6518112 (2003-02-01), Armacost et al.
patent: 6602745 (2003-08-01), Thwaite et al.
patent: 6660180 (2003-12-01), Lee et al.
patent: 6686214 (2004-02-01), Antaki et al.
patent: 6713341 (2004-03-01), Chen et al.
patent: 6784076 (2004-08-01), Gonzalez et al.
patent: 6808994 (2004-10-01), Wang
patent: 6858903 (2005-02-01), Natzle et al.
patent: 6881622 (2005-04-01), Yu et al.
patent: 6902962 (2005-06-01), Yeo et al.
patent: 6909147 (2005-06-01), Aller et al.
patent: 6927104 (2005-08-01), Lee et al.
patent: 6960507 (2005-11-01), Kim et al.
patent: 6960821 (2005-11-01), Noble et al.
patent: 6963114 (2005-11-01), Lin
patent: 6964903 (2005-11-01), Forbes et al.
patent: 6968110 (2005-11-01), Patel et al.
patent: 7045407 (2006-05-01), Keating et al.
patent: 2002/0001968 (2002-01-01), Lee et al.
patent: 2002/0025636 (2002-02-01), Ju
patent: 2003/0003759 (2003-01-01), Kudelka
patent: 2003/0022505 (2003-01-01), Ouellet et al.
patent: 2003/0057438 (2003-03-01), Yu et al.
patent: 2004/0014280 (2004-01-01), Willer et al.
patent: 2004/0038533 (2004-02-01), Liang
patent: 2004/0067346 (2004-04-01), Hofmann et al.
patent: 2004/0118805 (2004-06-01), Hareland et al.
patent: 2004/0214436 (2004-10-01), Dow
patent: 2005/0020091 (2005-01-01), Fucsko et al.
patent: 2005/0208727 (2005-09-01), Lin et al.
patent: 2007/0173007 (2007-07-01), Lee et al.
Sato “Development of Orientation Dependent Anisotropic Etching . . . ”; Electronics in communications in Japan, Part 2, vol. 83, No. 4, 2000; translated , vol. J82-C-11;No. 3, Mar. 1999; pp. 84-91.
E.Chen; Applied Physics 298r; Apr. 12, 2004; on mask orientation.
International Search Report dated Nov. 26, 2007, for International Application No. PCT/US2007/012904 (3 pages).
Bassous, Ernest, “Fabrication of Novel Three-Dimensional Microstructures by the Anisoptropic Etching of (100) and (110) Silicon,” IEEE Transactions on Electron Devices, Oct. 1978, pp. 1178-1185, vol. 25, No. 10.
Bean, Kenneth E., “Anisotropic Etching of Silicon,” IEEE Transactions on Electron Devices, Oct. 1978, pp. 1185-1193, vol. 25, No. 10.
Chu et al., “A Novel Convex Corner Compensation for Wet Anisotropic Etching on (100) Silicon Wafer,” Date Unknown, pp. 253-256.
Fried et al., “Improved Independent Gate N-Type FinFET Fabrication and Characterization,” IEEE Electron Device Letters, Sep. 2003, pp. 592-594, vol. 24, No. 9.
Huang et al., “Sub-50nm P-Channel FinFET,” IEEE Transactions on Electron Devices, May 2001, pp. 880-886, vol. 58, No. 5.
Jackson et al., “An Electrochemical P-N Junction Etch-Stop for the Formation of Silicon Microstructures,” IEEE Electron Device Letters, Feb. 1981, vol. EDL-2, No. 2.
Kim et al., “Advance Integration Technology for a Highly Scalable SOI DRAM with SOC (Silicon-On-Capacitors),” IEDM, 1996, pp. 605-608, vol. 96.
Lee et al., “Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for sub 60nm Technology and Beyond,” 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 130-131.
Lee et al., “A Novel Pattern Transfer Process for Bonded SOI Giga-bit DRAMS,” Proceedings 1996 IEEE International SOI Conference, Oct 1996, pp. 114-115.
Lee et al., “The Surface/Bulk Micromachining (SBM) Process: A New Method for Fabricating Released MEMS in Single Crystal Silicon,” Dec. 1999, vol. 8, No. 4.
Pandhumsoporn et al., “High Etch Rate, Deep Anistropic Plasma Etching of Silicon for MEMS Fabrication,” Date Unknown, pp. 1-9.
Wagner, Andrew, “KOH Si Wet Etch Review,” Date Unknown, pp. 1-14.
Yeo, et al., “80 nm 512M DRAM with Enhanced Data Retention Time Using Partially-Insulated Cell Array Transistor (PiCAT),” 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 30-31.
Yeo et al., Transistor test structures for leakage current analysis of partial SOI,: Date Unknown, 2 pages.

Affiliated with

Also associated with

Rating

Wet etch suitable for creating square cuts in si does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wet etch suitable for creating square cuts in si, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wet etch suitable for creating square cuts in si will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4142992