Well resistor for ESD protection of CMOS circuits

Details Well resistor for ESD protection of CMOS circuits Well resistor for ESD protection of CMOS circuits

1997-08-04

1999-03-09

Gaffin, Jeffrey

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 58, 361111, H02H 900

Patent

active

058809171

ABSTRACT:
A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.

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Winnerl, J., "Silicides for High-Density Memory and Logic Circuits", Semiconductor International, (4 pages) (Aug. 1994).

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